Brad's comments on the world of technology...

Blog Category: Hardware

Domain crossing techniques to avoid metastability in an FPGA

  I recently did some work on a working FPGA design.  It suffered from some classic clock domain crossing issue, but despite that it "worked".  But when stressed slightly it stopped working. I first wrote a classic verilog testbench.  I'll talk about those in an another post.  When I fixed the clock domain crossings the

Re-creating old CPU designs

Over the years I've done a number of experiments using Verilog, a hardware modeling language. In several of these experiments I have attempted to recreate old CPU designs like the MIT CADR lisp machine and the DEC PDP-8/I. My latest experiment is to recreate the PDP-11, in modern verlog, using modern simulation

Never Say Die... (reviving a Linksys WRT54GS)

A while back I did a project using the Linksys wireless routers. Well, more truthfully an associate did all the work, I just managed the project. Anyway, my associate, being rusty with hardware at that point managed to "brick" one of the units. It was toasted and would not respond to the simple recovery proceedure. (aside: I do this all the