I recently did some work on a working FPGA design. It suffered from some classic clock domain crossing issue, but despite that it "worked". But when stressed slightly it stopped working.
I first wrote a classic verilog testbench. I'll talk about those in an another post. When I fixed the clock domain crossings the FPGA failures went away.
- An excellent paper on metastability and techniques to avoid it
- Article on synchronizer-techniques-for-multi-clock-domain-SoCs
- A good paper on clock domain crossings
- Understanding Clock Domain Crossing Issues