Brad's comments on the world of technology...

Domain crossing techniques to avoid metastability in an FPGA


I recently did some work on a working FPGA design.  It suffered from some classic clock domain crossing issue, but despite that it "worked".  But when stressed slightly it stopped working.

I first wrote a classic verilog testbench.  I'll talk about those in an another post.  When I fixed the clock domain crossings the FPGA failures went away.


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