diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/Makefile linux-2.4.21-rmk1-s3c2800/arch/arm/Makefile --- linux-2.4.21-rmk1/arch/arm/Makefile Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/Makefile Thu Oct 16 10:33:11 2003 @@ -164,6 +164,10 @@ MACHINE = omaha endif +ifeq ($(CONFIG_ARCH_S3C2800),y) +MACHINE = s3c2800 +endif + export MACHINE PROCESSOR TEXTADDR GZFLAGS CFLAGS_BOOT OBJCOPYFLAGS # Only set INCDIR if its not already defined above diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/boot/Makefile linux-2.4.21-rmk1-s3c2800/arch/arm/boot/Makefile --- linux-2.4.21-rmk1/arch/arm/boot/Makefile Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/boot/Makefile Thu Oct 16 10:33:11 2003 @@ -117,6 +117,10 @@ ZRELADDR = 0x20008000 endif +ifeq ($(CONFIG_ARCH_S3C2800),y) +ZRELADDR = 0x08008000 +endif + # # We now have a PIC decompressor implementation. Decompressors running # from RAM should not define ZTEXTADDR. Decompressors running directly diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/boot/compressed/Makefile linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/Makefile --- linux-2.4.21-rmk1/arch/arm/boot/compressed/Makefile Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/Makefile Thu Oct 16 10:33:11 2003 @@ -71,6 +71,10 @@ OBJS += head-sa1100.o endif +ifeq ($(CONFIG_ARCH_S3C2800),y) +OBJS += head-s3c2800.o +endif + SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;s/BSS_START/$(ZBSSADDR)/ LIBGCC := $(shell $(CC) $(CFLAGS) --print-libgcc-file-name) diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/boot/compressed/head-s3c2800.S linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/head-s3c2800.S --- linux-2.4.21-rmk1/arch/arm/boot/compressed/head-s3c2800.S Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/head-s3c2800.S Sat Oct 18 06:59:13 2003 @@ -0,0 +1,206 @@ +/* + * linux/arch/arm/boot/compressed/head-s3c2800.S + * + * Samsung s3c2800 cpu + * + * Author: Brad Parker + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include +#include + + .section ".start", #alloc, #execinstr + +/* values for 200Mhz operation in PLLCON */ +/* S3C2800; ext clk=10Mhz, fclk=203Mhz, pclk=50.75Mhz */ +#define MDIV 0x5c +#define PDIV 0x3 +#define SDIV 0x0 + +/* registers */ +#define INTMOD 0x10020004 +#define INTMSK 0x10020008 +#define WTCON 0x10120004 + +#define PCONF 0x1010003c +#define PDATF 0x10100040 +#define PUPF 0x10100044 + +#define PLLCON 0x10000000 +#define CLKCON 0x10000004 +#define LOCKTIME 0x1000000c +#define SMBCON0 0x10010004 +#define SMBCON1 0x10010008 +#define SMBCON2 0x1001000c +#define SMBCON3 0x10010010 +#define REFRESH 0x10010014 +#define DMTMCON 0x10010018 +#define MRSR 0x1001001c + +/* clkcon bits */ +#define CLKCON_PCLK (1 << 12) +#define CLKCON_HCLK (1 << 11) + +/***************************************/ + + +#define BOOT_PROM_MISSING /* if boot prom is not programmed */ +#define CONFIG_S3C2800_CAMELOT_LED /* show progress on led's */ + +#define LED_LOOP_DELAY 0x00010000 + +__S3C2800_start: + + @ Preserve r8/r7 i.e. kernel entry values + +#if defined(CONFIG_MACH_FUJITSU_CAMELOT) + mov r7, #(MACH_TYPE_FUJITSU_CAMELOT&0xff) + orr r7, r7, #(MACH_TYPE_FUJITSU_CAMELOT&0xff00) + mov r8, #0 +#endif + + ldr r0,=WTCON /* disable watch dog reset */ + ldr r1,=0xa5 + str r1,[r0] + + ldr r0,=INTMSK + ldr r1,=0x0 /* mask all interrupts */ + str r1,[r0] + + ldr r0, =PCONF /* init portf for leds */ + ldr r1, =0x55aa + str r1, [r0] + + ldr r0, =PUPF /* disable pullups */ + ldr r1, =0xff + str r1, [r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0x10 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* h=f/2, p=h/2, turn all the clocks on */ + ldr r0,=CLKCON + ldr r1,=(CLKCON_PCLK | CLKCON_HCLK | 0x7fc) +/* ldr r1,=0x1ffc*/ + str r1,[r0] + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + ldr r0,=LOCKTIME + ldr r1,=0xffffff + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xf0 + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x20 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* configure PLL */ + ldr r0,=PLLCON + ldr r1,=((MDIV<<12)+(PDIV<<4)+SDIV) + str r1,[r0] + + /* some delay after setting pll */ + mov r0,#8000 +1: + subs r0,r0,#1 + bne 1b + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xf0 + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x30 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* + * this code should be removed once a boot prom is in place which + * will setup the memory timing and chip selects... + */ +#ifdef BOOT_PROM_MISSING + /* boot prom should do this but we don't have one yet */ + ldr r0,=SMBCON0 + ldr r1,=0x0001589 + str r1,[r0] + + ldr r0,=SMBCON1 + ldr r1,=0x0001589 + str r1,[r0] + + ldr r0,=SMBCON2 + ldr r1,=0x00101582 + str r1,[r0] + + ldr r0,=SMBCON3 + ldr r1,=0x00101580 + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xff + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x40 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* set up sdram timing (again, boot prom...) */ + ldr r0,=REFRESH + ldr r1,=0x008201e9 + str r1,[r0] + + ldr r0,=DMTMCON + ldr r1,=0x00010d10 + str r1,[r0] + + ldr r0,=MRSR + ldr r1,=0x00000020 + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xff + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x50 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + +#endif /* BOOT_PROM_MISSING */ + + b 1f + + .pool + + .align 8 + +1: + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/boot/compressed/head.S linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/head.S --- linux-2.4.21-rmk1/arch/arm/boot/compressed/head.S Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/boot/compressed/head.S Thu Oct 16 10:33:11 2003 @@ -253,6 +253,12 @@ cmp r0, r5 bls wont_overwrite +#ifdef CONFIG_ARCH_S3C2800 + @ when we boot out of flash we're running in low memory + @ and the test above fails... + b wont_overwrite +#endif + mov r5, r2 @ decompress after malloc space mov r0, r5 mov r3, r7 diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/config.in linux-2.4.21-rmk1-s3c2800/arch/arm/config.in --- linux-2.4.21-rmk1/arch/arm/config.in Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/config.in Sat Oct 18 06:59:03 2003 @@ -47,6 +47,7 @@ Motorola-MX1ADS CONFIG_ARCH_MX1ADS \ RiscPC CONFIG_ARCH_RPC \ RiscStation CONFIG_ARCH_RISCSTATION \ + S3C2800-based CONFIG_ARCH_S3C2800 \ SA1100-based CONFIG_ARCH_SA1100 \ Shark CONFIG_ARCH_SHARK \ AT91RM9200-based CONFIG_ARCH_AT91RM9200 " RiscPC @@ -181,6 +182,11 @@ endmenu +mainmenu_option next_comment +comment 'Samsung S3C2800 Implementations' +dep_bool ' Fujitsu Camelot' CONFIG_MACH_FUJITSU_CAMELOT $CONFIG_ARCH_S3C2800 +endmenu + # Definitions to make life easier if [ "$CONFIG_ARCH_ARCA5K" = "y" -o \ "$CONFIG_ARCH_RPC" = "y" ]; then @@ -300,7 +306,8 @@ # ARM920T if [ "$CONFIG_ARCH_MX1ADS" = "y" -o \ - "$CONFIG_ARCH_AT91RM9200" = "y" ]; then + "$CONFIG_ARCH_AT91RM9200" = "y" -o \ + "$CONFIG_ARCH_S3C2800" = "y" ]; then define_bool CONFIG_CPU_ARM920T y else if [ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \ @@ -378,7 +385,8 @@ "$CONFIG_ARCH_INTEGRATOR" = "y" -o "$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_L7200" = "y" -o "$CONFIG_ARCH_ANAKIN" = "y" -o \ "$CONFIG_ARCH_CAMELOT" = "y" -o "$CONFIG_ARCH_MX1ADS" = "y" -o \ - "$CONFIG_ARCH_OMAHA" = "y" -o "$CONFIG_ARCH_AT91RM9200" = "y" ]; then + "$CONFIG_ARCH_OMAHA" = "y" -o "$CONFIG_ARCH_AT91RM9200" = "y" -o \ + "$CONFIG_ARCH_S3C2800" = "y" ]; then define_bool CONFIG_CPU_32v4 y else define_bool CONFIG_CPU_32v4 n @@ -446,7 +454,8 @@ "$CONFIG_ARCH_EBSA110" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_EDB7211" = "y" -o \ - "$CONFIG_ARCH_SA1100" = "y" ]; then + "$CONFIG_ARCH_SA1100" = "y" -o \ + "$CONFIG_ARCH_S3C2800" = "y" ]; then define_bool CONFIG_ISA y else define_bool CONFIG_ISA n @@ -514,7 +523,8 @@ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_P720T" = "y" -o \ - "$CONFIG_ARCH_OMAHA" = "y" ]; then + "$CONFIG_ARCH_OMAHA" = "y" -o \ + "$CONFIG_ARCH_S3C2800" = "y" ]; then bool 'Timer and CPU usage LEDs' CONFIG_LEDS if [ "$CONFIG_LEDS" = "y" ]; then if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ @@ -524,7 +534,8 @@ "$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_P720T" = "y" -o \ - "$CONFIG_ARCH_OMAHA" = "y" ]; then + "$CONFIG_ARCH_OMAHA" = "y" -o \ + "$CONFIG_MACH_FUJITSU_CAMELOT" = "y" ]; then bool ' Timer LED' CONFIG_LEDS_TIMER bool ' CPU usage LED' CONFIG_LEDS_CPU fi diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/head-s3c2800.S linux-2.4.21-rmk1-s3c2800/arch/arm/head-s3c2800.S --- linux-2.4.21-rmk1/arch/arm/head-s3c2800.S Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/head-s3c2800.S Sat Oct 18 06:59:30 2003 @@ -0,0 +1,206 @@ +/* + * linux/arch/arm/boot/compressed/head-s3c2800.S + * + * Samsung s3c2800 cpu + * + * Author: Brad Parker + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include +#include + + .section ".start", #alloc, #execinstr + +/* values for 200Mhz operation in PLLCON */ +/* S3C2800; ext clk=10Mhz, fclk=203Mhz, pclk=50.75Mhz */ +#define MDIV 0x5c +#define PDIV 0x3 +#define SDIV 0x0 + +/* registers */ +#define INTMOD 0x10020004 +#define INTMSK 0x10020008 +#define WTCON 0x10120004 + +#define PCONF 0x1010003c +#define PDATF 0x10100040 +#define PUPF 0x10100044 + +#define PLLCON 0x10000000 +#define CLKCON 0x10000004 +#define LOCKTIME 0x1000000c +#define SMBCON0 0x10010004 +#define SMBCON1 0x10010008 +#define SMBCON2 0x1001000c +#define SMBCON3 0x10010010 +#define REFRESH 0x10010014 +#define DMTMCON 0x10010018 +#define MRSR 0x1001001c + +/* clkcon bits */ +#define CLKCON_PCLK (1 << 12) +#define CLKCON_HCLK (1 << 11) + +/***************************************/ + + +#define BOOT_PROM_MISSING /* if boot prom is not programmed */ +#define CONFIG_S3C2800_CAMELOT_LED /* show progress on led's */ + +#define LED_LOOP_DELAY 0x00010000 + +__S3C2800_start: + + @ Preserve r8/r7 i.e. kernel entry values + +#if defined(CONFIG_MACH_FUJITSU_CAMELOT) + mov r7, #(MACH_TYPE_FUJITSU_CAMELOT&0xff) + orr r7, r7, #(MACH_TYPE_FUJITSU_CAMELOT&0xff00) + mov r8, #0 +#endif + + ldr r0,=WTCON /* disable watch dog reset */ + ldr r1,=0xa5 + str r1,[r0] + + ldr r0,=INTMSK + ldr r1,=0x0 /* mask all interrupts */ + str r1,[r0] + + ldr r0, =PCONF /* init portf for leds */ + ldr r1, =0x55aa + str r1, [r0] + + ldr r0, =PUPF /* disable pullups */ + ldr r1, =0xff + str r1, [r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0x10 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* h=f/2, p=h/2, turn all the clocks on */ + ldr r0,=CLKCON + ldr r1,=(CLKCON_PCLK | CLKCON_HCLK | 0x7fc) +/* ldr r1,=0x1ffc*/ + str r1,[r0] + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + ldr r0,=LOCKTIME + ldr r1,=0xffffff + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xf0 + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x20 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* configure PLL */ + ldr r0,=PLLCON + ldr r1,=((MDIV<<12)+(PDIV<<4)+SDIV) + str r1,[r0] + + /* some delay after setting pll */ + mov r0,#8000 +1: + subs r0,r0,#1 + bne 1b + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xf0 + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x30 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* + * this code should be removed once a boot prom is in place which + * will setup the memory timing and chip selects... + */ +#ifdef BOOT_PROM_MISSING + /* boot prom should do this but we don't have one yet */ + ldr r0,=SMBCON0 + ldr r1,=0x0001589 + str r1,[r0] + + ldr r0,=SMBCON1 + ldr r1,=0x0001589 + str r1,[r0] + + ldr r0,=SMBCON2 + ldr r1,=0x00101582 + str r1,[r0] + + ldr r0,=SMBCON3 + ldr r1,=0x00101580 + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xff + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x40 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + + /* set up sdram timing (again, boot prom...) */ + ldr r0,=REFRESH + ldr r1,=0x008201e9 + str r1,[r0] + + ldr r0,=DMTMCON + ldr r1,=0x00010d10 + str r1,[r0] + + ldr r0,=MRSR + ldr r1,=0x00000020 + str r1,[r0] + +#if defined(CONFIG_S3C2800_CAMELOT_LED) + ldr r0, =PDATF + ldr r1, =0xff + str r1, [r0] + ldr r0, =PDATF + ldr r1, =0x50 + str r1, [r0] + mov r0, #LED_LOOP_DELAY +1: subs r0, r0, #1 + bne 1b +#endif + +#endif /* BOOT_PROM_MISSING */ + + b 1f + + .pool + + .align 8 + +1: + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/kernel/Makefile linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/Makefile --- linux-2.4.21-rmk1/arch/arm/kernel/Makefile Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/Makefile Thu Oct 16 10:42:38 2003 @@ -45,7 +45,7 @@ $(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \ $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT) \ $(CONFIG_ARCH_MX1ADS) $(CONFIG_ARCH_OMAHA) \ - $(CONFIG_ARCH_AT91RM9200) + $(CONFIG_ARCH_AT91RM9200) $(CONFIG_ARCH_S3C2800) ifneq ($(findstring y,$(no-irq-arch)),y) obj-y += irq-arch.o diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/kernel/entry-armv.S linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/entry-armv.S --- linux-2.4.21-rmk1/arch/arm/kernel/entry-armv.S Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/entry-armv.S Thu Oct 16 10:33:11 2003 @@ -615,6 +615,52 @@ .text .endm +#elif defined(CONFIG_ARCH_S3C2800) + + .macro disable_fiq + .endm + /* r0 r6 r5 lr */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \irqstat, #VA_INT_BASE&0xff000000 @ IO Base add virtual + add \irqstat, \irqstat, #VA_INT_BASE&0x00ff0000 + + ldr \irqstat, [\irqstat, #0xc] @ get interrupts bits + + cmp \irqstat, #0 + mov \irqnr, #0 @ if zero, bail out + beq 1001f + + @ + @ find first bit set... + @ turn lowest bit set into binary number, 0..31 + @ + @ shift bytes down until low byte is non-zero, + @ then subdivide bits in half until we find one which is set + @ + tst \irqstat, #0xff @ check lowest byte + moveq \irqstat, \irqstat, lsr #8 @ if zero, shift down 8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff @ try again + moveq \irqstat, \irqstat, lsr #8 @ if zero, shift down 8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff @ try again + moveq \irqstat, \irqstat, lsr #8 @ if zero, shift down 8 + addeq \irqnr, \irqnr, #8 + tst \irqstat, #0x0f @ ok, bit 0-7 set + moveq \irqstat, \irqstat, lsr #4 @ if low nib==0, shift + addeq \irqnr, \irqnr, #4 + tst \irqstat, #0x03 @ ok, bit 0-3 set + moveq \irqstat, \irqstat, lsr #2 @ if 0-1 == 0, shift + addeq \irqnr, \irqnr, #2 + tst \irqstat, #0x01 @ low bit set? + addeqs \irqnr, \irqnr, #1 @ if not, it's bit 1 +1001: + .endm + + .macro irq_prio_table + .endm + #else #error Unknown architecture #endif diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/kernel/head-armv.S linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/head-armv.S --- linux-2.4.21-rmk1/arch/arm/kernel/head-armv.S Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/kernel/head-armv.S Thu Oct 16 10:33:11 2003 @@ -131,6 +131,12 @@ mov r1, #MACH_TYPE_L7200 #endif +#if defined(CONFIG_ARCH_S3C2800) +/* FIXME - No bootloader, so manually set 'r1' with our architecture number. */ + mov r1, #(MACH_TYPE_FUJITSU_CAMELOT&0xff) + orr r1, r1, #(MACH_TYPE_FUJITSU_CAMELOT&0xff00) +#endif + mov r0, #F_BIT | I_BIT | MODE_SVC @ make sure svc mode msr cpsr_c, r0 @ and all irqs disabled bl __lookup_processor_type diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/arch/arm/tools/mach-types linux-2.4.21-rmk1-s3c2800/arch/arm/tools/mach-types --- linux-2.4.21-rmk1/arch/arm/tools/mach-types Thu Oct 16 10:10:08 2003 +++ linux-2.4.21-rmk1-s3c2800/arch/arm/tools/mach-types Sat Oct 18 07:01:15 2003 @@ -363,3 +363,4 @@ ixrd425 ARCH_IXRD425 IXRD425 352 iq80315 ARCH_IQ80315 IQ80315 353 nmp7312 ARCH_NMP7312 NMP7312 354 +fujitsu_camelot MACH_FUJITSU_CAMELOT FUJITSU_CAMELOT 391 diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/drivers/serial/Config.in linux-2.4.21-rmk1-s3c2800/drivers/serial/Config.in --- linux-2.4.21-rmk1/drivers/serial/Config.in Thu Oct 16 10:10:09 2003 +++ linux-2.4.21-rmk1-s3c2800/drivers/serial/Config.in Thu Oct 16 10:52:21 2003 @@ -43,6 +43,11 @@ dep_tristate 'AT91RM9200 serial port support' CONFIG_SERIAL_AT91 $CONFIG_ARCH_AT91RM9200 dep_bool ' Console on AT91RM9200 serial port' CONFIG_SERIAL_AT91_CONSOLE $CONFIG_SERIAL_AT91 + dep_tristate 'S3C2800 serial port support' CONFIG_SERIAL_S3C2800 $CONFIG_ARCH_S3C2800 + dep_bool ' Console on S3C2800 serial port' CONFIG_SERIAL_S3C2800_CONSOLE $CONFIG_SERIAL_S3C2800 + if [ "$CONFIG_SERIAL_S3C2800" = "y" ]; then + int ' Default S3C2800 serial baudrate' CONFIG_S3C2800_DEFAULT_BAUDRATE 115200 + fi fi # # The new 8250/16550 serial drivers @@ -63,7 +68,8 @@ "$CONFIG_SERIAL_UART00" = "y" -o \ "$CONFIG_SERIAL_8250" = "y" -o \ "$CONFIG_SERIAL_OMAHA" = "y" -o \ - "$CONFIG_SERIAL_AT91" = "y" ]; then + "$CONFIG_SERIAL_AT91" = "y" -o \ + "$CONFIG_SERIAL_S3C2800" = "y" ]; then define_bool CONFIG_SERIAL_CORE y else if [ "$CONFIG_SERIAL_AMBA" = "m" -o \ @@ -73,7 +79,8 @@ "$CONFIG_SERIAL_UART00" = "m" -o \ "$CONFIG_SERIAL_8250" = "m" -o \ "$CONFIG_SERIAL_OMAHA" = "m" -o \ - "$CONFIG_SERIAL_AT91" = "m" ]; then + "$CONFIG_SERIAL_AT91" = "m" -o \ + "$CONFIG_SERIAL_S3C2800" = "m" ]; then define_bool CONFIG_SERIAL_CORE m fi fi @@ -84,7 +91,8 @@ "$CONFIG_SERIAL_UART00_CONSOLE" = "y" -o \ "$CONFIG_SERIAL_8250_CONSOLE" = "y" -o \ "$CONFIG_SERIAL_OMAHA" = "y" -o \ - "$CONFIG_SERIAL_AT91_CONSOLE" = "y" ]; then + "$CONFIG_SERIAL_AT91_CONSOLE" = "y" -o \ + "$CONFIG_SERIAL_S3C2800_CONSOLE" = "y" ]; then define_bool CONFIG_SERIAL_CORE_CONSOLE y fi diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/drivers/serial/Makefile linux-2.4.21-rmk1-s3c2800/drivers/serial/Makefile --- linux-2.4.21-rmk1/drivers/serial/Makefile Thu Oct 16 10:10:09 2003 +++ linux-2.4.21-rmk1-s3c2800/drivers/serial/Makefile Thu Oct 16 10:55:09 2003 @@ -32,6 +32,7 @@ obj-$(CONFIG_SERIAL_UART00) += uart00.o obj-$(CONFIG_SERIAL_OMAHA) += omaha.o obj-$(CONFIG_SERIAL_AT91US3) += at91us3.o +obj-$(CONFIG_SERIAL_S3C2800) += s3c2800.o include $(TOPDIR)/Rules.make diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/drivers/serial/core.c linux-2.4.21-rmk1-s3c2800/drivers/serial/core.c --- linux-2.4.21-rmk1/drivers/serial/core.c Thu Oct 16 10:10:09 2003 +++ linux-2.4.21-rmk1-s3c2800/drivers/serial/core.c Thu Oct 16 10:55:50 2003 @@ -1939,6 +1939,7 @@ extern void sa1100_rs_console_init(void); extern void serial8250_console_init(void); extern void at91_console_init(void); +extern void s3c2800uart_console_init(void); /* * Central "initialise all serial consoles" container. Needs to be killed. @@ -1966,6 +1967,9 @@ #ifdef CONFIG_SERIAL_UART00_CONSOLE uart00_console_init(); #endif +#ifdef CONFIG_SERIAL_S3C2800_CONSOLE + s3c2800uart_console_init(); +#endif } #endif /* CONFIG_SERIAL_CORE_CONSOLE */ diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/drivers/serial/s3c2800.c linux-2.4.21-rmk1-s3c2800/drivers/serial/s3c2800.c --- linux-2.4.21-rmk1/drivers/serial/s3c2800.c Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/drivers/serial/s3c2800.c Thu Oct 16 12:46:14 2003 @@ -0,0 +1,677 @@ +/* + * linux/drivers/char/serial_s3c2800.c + * + * Driver for Samsung S3C2800's internal serial ports (UART0 & UART1) + * + * Based on Steve Hein's S3C2410 driver, Brad parker (brad@heeltoe.com) + * + * Copyright (C) 2002 Steve Hein, SGI Inc. (ssh@sgi.com) + * + * Adapted from: + * + * Driver for MX1s' dual serial ports. + * + * Based on drivers/serial/serial_amba.c + * + * + * Copyright 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * Based on the AMBA driver, this is a driver for the S3C2800 boards + * UARTs. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if defined(CONFIG_SERIAL_S3C2800_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include + +#include + +#define UART_NR 2 + +#define MINOR_START 64 + +#define SERIAL_S3C2800_NAME "ttyS" +#define SERIAL_S3C2800_MAJOR TTY_MAJOR +#define SERIAL_S3C2800_MINOR MINOR_START +#define SERIAL_S3C2800_NR UART_NR + +#define CALLOUT_S3C2800_NAME "cuas" +#define CALLOUT_S3C2800_MAJOR 205 +#define CALLOUT_S3C2800_MINOR MINOR_START +#define CALLOUT_S3C2800_NR UART_NR + + +static struct tty_driver normal, callout; +static struct tty_struct *s3c2800_table[UART_NR]; +static struct termios *s3c2800_termios[UART_NR], *s3c2800_termios_locked[UART_NR]; +#ifdef SUPPORT_SYSRQ +static struct console s3c2800_console; +#endif + +#define S3C2800_ISR_PASS_LIMIT 256 + +/* + * Access macros for the S3C2800 UARTs + */ + +#define UART_GET_CHAR(p) __raw_readb((p)->membase + S3C2800_UARTRXH0_OFF) +#define UART_PUT_CHAR(p,c) __raw_writeb((c), (p)->membase + S3C2800_UARTTXH0_OFF) + +#define UART_GET_ULCON(p) __raw_readl((p)->membase + S3C2800_UARTLCON_OFF) +#define UART_GET_UCON(p) __raw_readl((p)->membase + S3C2800_UARTCON_OFF) +#define UART_GET_UFCON(p) __raw_readl((p)->membase + S3C2800_UARTFCON_OFF) +#define UART_GET_UMCON(p) __raw_readl((p)->membase + S3C2800_UARTMCON_OFF) +#define UART_GET_UBRDIV(p) __raw_readl((p)->membase + S3C2800_UARTBRDIV_OFF) + +#define UART_GET_UTRSTAT(p) __raw_readl((p)->membase + S3C2800_UARTTRSTAT_OFF) +#define UART_GET_UERSTAT(p) __raw_readl((p)->membase + S3C2800_UARTERSTAT_OFF) +#define UART_GET_UFSTAT(p) __raw_readl((p)->membase + S3C2800_UARTFSTAT_OFF) +#define UART_GET_UMSTAT(p) __raw_readl((p)->membase + S3C2800_UARTMSTAT_OFF) + +#define UART_PUT_ULCON(p,c) __raw_writel(c, (p)->membase + S3C2800_UARTLCON_OFF) +#define UART_PUT_UCON(p,c) __raw_writel(c, (p)->membase + S3C2800_UARTCON_OFF) +#define UART_PUT_UFCON(p,c) __raw_writel(c, (p)->membase + S3C2800_UARTFCON_OFF) +#define UART_PUT_UMCON(p,c) __raw_writel(c, (p)->membase + S3C2800_UARTMCON_OFF) +#define UART_PUT_UBRDIV(p,c) __raw_writel(c, (p)->membase + S3C2800_UARTBRDIV_OFF) + + +/* When using the integer divisor for the UART, + * we must set the IR to 0xf prior to programming + * the divisor + */ + + +#define UART_RX_DATA(s) (((s) & S3C2800_UTRSTAT_RXDR) == S3C2800_UTRSTAT_RXDR) +#define UART_TX_READY(s) (((s) & S3C2800_UTRSTAT_TXFE) == S3C2800_UTRSTAT_TXFE) +#define TX_FIFOCOUNT(port) (((UART_GET_UFSTAT(port))>>4)&0xf) + +#define TX_IRQ(port) (port->irq + 2) +#define RX_IRQ(port) (port->irq) + +#define tx_enabled(port) ((port)->unused[0]) + +#define UART_DUMMY_RSR_RX 256 +#define UART_PORT_SIZE 64 + +/* + * Our private driver data mappings. + */ + +//#define drv_old_status driver_priv + +static void +s3c2800uart_stop_tx(struct uart_port *port, u_int from_tty) +{ + if (tx_enabled(port)) { + disable_irq(TX_IRQ(port)); + tx_enabled(port) = 0; + } +} + +static void +s3c2800uart_start_tx(struct uart_port *port, unsigned int tty_start + /*u_int nonempty, u_int from_tty*/) +{ + if (/*nonempty && */!tx_enabled(port)) { + enable_irq(TX_IRQ(port)); + tx_enabled(port) = 1; + } +} + +static void +s3c2800uart_stop_rx(struct uart_port *port) +{ + disable_irq(RX_IRQ(port)); +} + +static void +s3c2800uart_enable_ms(struct uart_port *port) +{ + /* What is MS? */ +} + +static void +#ifdef SUPPORT_SYSRQ +s3c2800uart_rx_chars(struct uart_port *port, struct pt_regs *regs) +#else +s3c2800uart_rx_chars(struct uart_port *port) +#endif +{ + struct tty_struct *tty = port->info->tty; + unsigned int status, ch, max_count = 256; + + status = UART_GET_UTRSTAT(port); + while (UART_RX_DATA(status) && max_count--) { + if (tty->flip.count >= TTY_FLIPBUF_SIZE) { + tty->flip.tqueue.routine((void *) tty); + if (tty->flip.count >= TTY_FLIPBUF_SIZE) { + printk(KERN_WARNING "TTY_DONT_FLIP set\n"); + return; + } + } + + ch = UART_GET_CHAR(port); + + *tty->flip.char_buf_ptr = ch; + *tty->flip.flag_buf_ptr = TTY_NORMAL; + port->icount.rx++; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + /* No error handling just yet. + * On the MX1 these are seperate + * IRQs, so we need to deal with + * the sanity of 5 IRQs for one + * serial port before we deal + * with the error path properly. + */ + status = UART_GET_UTRSTAT(port); + } + tty_flip_buffer_push(tty); + return; +} + +static void +s3c2800uart_tx_chars(struct uart_port *port) +{ + struct uart_info *info = port->info; + int count; + + if (port->x_char) { + UART_PUT_CHAR(port, port->x_char); + port->icount.tx++; + port->x_char = 0; + return; + } + if (info->xmit.head == info->xmit.tail + || info->tty->stopped || info->tty->hw_stopped) { + s3c2800uart_stop_tx(port, 0); + return; + } + + count = port->fifosize - TX_FIFOCOUNT(port); + do { + UART_PUT_CHAR(port, info->xmit.buf[info->xmit.tail]); + info->xmit.tail = (info->xmit.tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (info->xmit.head == info->xmit.tail) + break; + } while (--count > 0); + + if (CIRC_CNT(info->xmit.head, info->xmit.tail, UART_XMIT_SIZE) < + WAKEUP_CHARS) + uart_write_wakeup(port); + + if (info->xmit.head == info->xmit.tail) + s3c2800uart_stop_tx(port, 0); +} + +static void +s3c2800uart_modem_status(struct uart_port *port) +{ + /* + * Not currently supported. + * + */ +} + +static void +s3c2800uart_int(int irq, void *dev_id, struct pt_regs *regs) +{ + struct uart_port *port = dev_id; + unsigned int status; + + status = UART_GET_UTRSTAT(port); + if(irq==(TX_IRQ(port))) { + if (UART_TX_READY(status)) + s3c2800uart_tx_chars(port); + } + + if (UART_RX_DATA(status)) { +#ifdef SUPPORT_SYSRQ + s3c2800uart_rx_chars(port, regs); +#else + s3c2800uart_rx_chars(port); +#endif + } +} + +static u_int +s3c2800uart_tx_empty(struct uart_port *port) +{ + return UART_GET_UTRSTAT(port) & S3C2800_UTRSTAT_TXFE ? TIOCSER_TEMT : 0; +} + +static u_int +s3c2800uart_get_mctrl(struct uart_port *port) +{ + /* Not currently supported */ + return 0; +} + +static void +s3c2800uart_set_mctrl(struct uart_port *port, u_int mctrl) +{ + /* Not currently supported */ +} + +static void +s3c2800uart_break_ctl(struct uart_port *port, int break_state) +{ + unsigned long ucon=UART_GET_UCON(port); + ucon |= S3C2800_UCON_SBREAK; + UART_PUT_UCON(port,ucon); +} + +static int +s3c2800uart_startup(struct uart_port *port) +{ + int retval; + + tx_enabled(port) = 1; + + /* + * Allocate the IRQ + */ +#ifdef DEBUG + printk("s3c2800uart_startup() %d %d; port->membase %p\n", + RX_IRQ(port), TX_IRQ(port), info->port->membase); +#endif + + retval = request_irq(RX_IRQ(port), s3c2800uart_int, 0, "s3c2800uarx", + port); + if (retval) + return retval; + + retval = request_irq(TX_IRQ(port), s3c2800uart_int, 0, "s3c2800uatx", + port); + if (retval) + return retval; + + UART_PUT_UCON(port, S3C2800_UCON_DEFAULT); + + UART_PUT_UFCON(port, S3C2800_UFCON_DEFAULT); + + UART_PUT_UMCON(port, 0); + + UART_PUT_UBRDIV(port, (int)((PCLK/(CURRENT_BAUD_RATE*16)))-1); + + return 0; + +} + +static void +s3c2800uart_shutdown(struct uart_port *port) +{ + /* + * Free the interrupt + */ + free_irq(RX_IRQ(port), port); + free_irq(TX_IRQ(port), port); +} + +static void +s3c2800uart_change_speed(struct uart_port *port, u_int cflag, u_int iflag, + u_int quot) +{ + unsigned long flags, lcon; +#if DEBUG + printk("s3c2800uart_set_cflag(0x%x) called\n", cflag); +#endif + + /* first, disable everything */ + save_flags(flags); + cli(); + lcon=UART_GET_ULCON(port); + /* Clear the bits we're going to configure */ + lcon &= ~(S3C2800_LCON_CFGMASK); + + switch (cflag & CSIZE) { + case CS5: + lcon |= S3C2800_LCON_CS5; + break; + case CS6: + lcon |= S3C2800_LCON_CS6; + break; + case CS7: + lcon |= S3C2800_LCON_CS7; + break; + default: + lcon |= S3C2800_LCON_CS8; + break; + } + if(cflag & PARENB) { + lcon |= (cflag & PARODD)? S3C2800_LCON_PODD:S3C2800_LCON_PEVEN; + } else { + lcon |= S3C2800_LCON_PNONE; + } + + UART_PUT_ULCON(port, lcon); + if(iflag & BRKINT) { + unsigned long ucon=UART_GET_UCON(port); + ucon |= S3C2800_UCON_SBREAK; + UART_PUT_UCON(port, ucon); + } + + restore_flags(flags); + +} + +static const char * +s3c2800uart_type(struct uart_port *port) +{ + return port->type == PORT_S3C2800 ? "S3C2800" : NULL; +} + +/* + * Release the memory region(s) being used by 'port'. + */ +static void +s3c2800uart_release_port(struct uart_port *port) +{ + return; +} + +/* + * Request the memory region(s) being used by 'port'. + */ +static int +s3c2800uart_request_port(struct uart_port *port) +{ + return 0; +} + +/* + * Configure/autoconfigure the port. + */ +static void +s3c2800uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE && s3c2800uart_request_port(port) == 0) + port->type = PORT_S3C2800; +} + +static int +s3c2800uart_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + return 0; +} + +static struct uart_ops s3c2800_pops = { + tx_empty: s3c2800uart_tx_empty, + set_mctrl: s3c2800uart_set_mctrl, + get_mctrl: s3c2800uart_get_mctrl, + stop_tx: s3c2800uart_stop_tx, + start_tx: s3c2800uart_start_tx, + stop_rx: s3c2800uart_stop_rx, + enable_ms: s3c2800uart_enable_ms, + break_ctl: s3c2800uart_break_ctl, + startup: s3c2800uart_startup, + shutdown: s3c2800uart_shutdown, + change_speed: s3c2800uart_change_speed, + type: s3c2800uart_type, + release_port: s3c2800uart_release_port, + request_port: s3c2800uart_request_port, + config_port: s3c2800uart_config_port, + verify_port: s3c2800uart_verify_port, +}; + +static struct uart_port s3c2800_ports[UART_NR] = { + { + membase: (void *) VA_UART_BASE, + mapbase: VA_UART_BASE, + iotype: SERIAL_IO_MEM, + irq: IRQ_RXD0, + uartclk: 130252800, + fifosize: 16, + unused: {4, 5}, + ops: &s3c2800_pops, + type: PORT_S3C2800, + flags: ASYNC_BOOT_AUTOCONF, + }, + { + membase: (void *) (VA_UART_BASE + S3C2800_UART1_OFF), + mapbase: (VA_UART_BASE + S3C2800_UART1_OFF), + iotype: SERIAL_IO_MEM, + irq: IRQ_RXD1, + uartclk: 130252800, + fifosize: 16, + unused: {6, 7}, + ops: &s3c2800_pops, + type: PORT_S3C2800, + flags: ASYNC_BOOT_AUTOCONF, + } +}; + +#ifdef CONFIG_SERIAL_S3C2800_CONSOLE + +#ifdef used_and_not_const_char_pointer +static int +s3c2800uart_console_read(struct uart_port *port, char *s, u_int count) +{ + unsigned int status; + int c; + +#if DEBUG + printk("s3c2800uart_console_read() called\n"); +#endif + + c = 0; + while (c < count) { + status = UART_GET_USR2(port); + if (UART_RX_DATA(status)) { + *s++ = UART_GET_CHAR(port); + c++; + } else { + // nothing more to get, return + return c; + } + } + // return the count + return c; +} +#endif + + +static void +s3c2800uart_console_write(struct console *co, const char *s, u_int count) +{ + struct uart_port *port = s3c2800_ports + co->index; + unsigned int status; + int i; + /* + * Now, do each character + */ + for (i = 0; i < count; i++) { + do { + status = UART_GET_UTRSTAT(port); + } while (!UART_TX_READY(status)); + UART_PUT_CHAR(port, (s[i]) & 0xff); + if (s[i] == '\n') { + do { + status = UART_GET_UTRSTAT(port); + } while (!UART_TX_READY(status)); + UART_PUT_CHAR(port, '\r'); + } + } +} + +static kdev_t +s3c2800uart_console_device(struct console *co) +{ + + return MKDEV(SERIAL_S3C2800_MAJOR, SERIAL_S3C2800_MINOR + co->index); +} + +#if 0 +static int +s3c2800uart_console_wait_key(struct console *co) +{ + struct uart_port *port = s3c2800_ports + co->index; + unsigned int status; + + do { + status = UART_GET_UTRSTAT(port); + } while (!UART_RX_DATA(status)); + return UART_GET_CHAR(port); +} +#endif + +static void __init +s3c2800uart_console_get_options(struct uart_port *port, int *baud, int *parity, + int *bits) +{ + *baud = CURRENT_BAUD_RATE; + *bits = 8; + *parity = 'n'; +} + +static int __init +s3c2800uart_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = CURRENT_BAUD_RATE; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + port = uart_get_console(s3c2800_ports, UART_NR, co); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + s3c2800uart_console_get_options(port, &baud, &parity, &bits); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console s3c2800_console = { + name: SERIAL_S3C2800_NAME, + write: s3c2800uart_console_write, +#ifdef used_and_not_const_char_pointer + read: s3c2800uart_console_read, +#endif + device: s3c2800uart_console_device, +// wait_key: s3c2800uart_console_wait_key, + setup: s3c2800uart_console_setup, + flags: CON_PRINTBUFFER, + index: -1, +}; + +void __init +s3c2800uart_console_init(void) +{ + register_console(&s3c2800_console); +} + +#define S3C2800_CONSOLE &s3c2800_console +#else +#define S3C2800_CONSOLE NULL +#endif + +static struct uart_driver s3c2800_reg = { + owner: THIS_MODULE, + normal_major: SERIAL_S3C2800_MAJOR, +#ifdef CONFIG_DEVFS_FS + normal_name: SERIAL_S3C2800_NAME "%d", + callout_name: CALLOUT_S3C2800_NAME "%d", +#else + normal_name: SERIAL_S3C2800_NAME, + callout_name: CALLOUT_S3C2800_NAME, +#endif + normal_driver :&normal, + callout_major: CALLOUT_S3C2800_MAJOR, + callout_driver: &callout, + table: s3c2800_table, + termios: s3c2800_termios, + termios_locked: s3c2800_termios_locked, + minor: SERIAL_S3C2800_MINOR, + nr: UART_NR, + cons: S3C2800_CONSOLE, +}; + +static int __init +s3c2800uart_init(void) +{ + int ret; + + ret = uart_register_driver(&s3c2800_reg); + if (ret == 0) { + int i; + + for (i = 0; i < UART_NR; i++) + uart_add_one_port(&s3c2800_reg, &s3c2800_ports[i]); + } + return ret; +} + +static void __exit +s3c2800uart_exit(void) +{ + int i; + + for (i = 0; i < UART_NR; i++) + uart_remove_one_port(&s3c2800_reg, &s3c2800_ports[i]); + + uart_unregister_driver(&s3c2800_reg); +} + +module_init(s3c2800uart_init); +module_exit(s3c2800uart_exit); + +EXPORT_NO_SYMBOLS; + +MODULE_AUTHOR("Brad Parker "); +MODULE_DESCRIPTION("Samsung S3C2800X01 serial port driver"); +MODULE_LICENSE("GPL"); diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/dma.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/dma.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/dma.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/dma.h Sat Oct 18 07:02:43 2003 @@ -0,0 +1,157 @@ +/* + * linux/include/asm-arm/arch-s3c2800/dma.h + * + * Generic S3C2800 DMA support + * + * Copyright (C) 2002 SW.LEE + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include +#include +#include + +#ifndef __ASM_S3C2800_ARCH_DMA_H +#define __ASM_S3C2800_ARCH_DMA_H + +/* + * This is the maximum DMA address(physical address) that can be DMAd to. + * + */ +#define MAX_DMA_ADDRESS 0x20000000 +#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ + +/* + * The regular generic DMA interface is inappropriate for the + * S3C2800 DMA model. None of the S3C2800 specific drivers using + * DMA are portable anyway so it's pointless to try to twist the + * regular DMA API to accommodate them. + */ + +/***************************************************************************/ +/* this means that We will use arch/arm/mach/dma.h i.e generic dma module */ +#define MAX_DMA_CHANNELS 0 +/****************************************************************************/ + +/* + * The S3C2800 has four internal DMA channels. + */ +#define S3C2800_DMA_CHANNELS 4 + +#define MAX_S3C2800_DMA_CHANNELS S3C2800_DMA_CHANNELS + + +/* + * All possible S3C2800 devices the specific DMA channel can be attached to. + * I'm sorry for only DMA Device Address + * DMA request sources would be controlled by H/W DMA mode selected by DCON register + */ + +typedef enum { + DMA0_SOURCE0 , /* NXDREQ0 */ + DMA0_SOURCE1 , /* UART0 */ + DMA0_SOURCE2 , /* MMC */ + DMA0_SOURCE3 , /* TIMER */ + DMA0_SOURCE4 , /* USB DEVICE EP1 */ + DMA1_SOURCE0 , /* NXDREQ1 */ + DMA1_SOURCE1 , /* UART1 */ + DMA1_SOURCE2 , /* I2SSDI */ + DMA1_SOURCE3 , /* SPI */ + DMA1_SOURCE4 , /* USB DEVICE EP2 */ + DMA2_SOURCE0/* = IISFIFO*/, /* I2SSD0 */ + DMA2_SOURCE1 , /* I2SSDI */ + DMA2_SOURCE2 , /* MMC */ + DMA2_SOURCE3 , /* TIMER */ + DMA2_SOURCE4 , /* USB DEVICE EP3 */ + DMA3_SOURCE0 , /* UART2 */ + DMA3_SOURCE1 , /* MMC */ + DMA3_SOURCE2 , /* SPI */ + DMA3_SOURCE3 , /* TIMER */ + DMA3_SOURCE4 , /* USB DEVICE EP4 */ +} dma_device_t; + + +/* + * DMA buffer structure + */ + +typedef struct dma_buf_s { + int size; /* buffer size */ + dma_addr_t dma_start; /* starting DMA address */ + dma_addr_t dma_ptr; /* next DMA pointer to use */ + int ref; /* number of DMA references */ + void *id; /* to identify buffer from outside */ + struct dma_buf_s *next; /* next buffer to process */ +} dma_buf_t; + + +/* + * DMA channel structure. + */ + +/* + * DMA control register structure + * one channel S3C2800 DMA control register is 0x40 byte + * + */ + +typedef void (*dma_callback_t)( void *buf_id, int size); + +typedef struct { + volatile u_long DISRC; + volatile u_long DISRCC; + volatile u_long DIDST; + volatile u_long DIDSTC; + volatile u_long DCON; + volatile u_long DSTAT; + volatile u_long DCSRC; + volatile u_long DCDST; + volatile u_long DMASKTRIG; +} dma_regs_t; + +#define DOUBLE_BUFFER_COUNT 3 +typedef struct { + unsigned int in_use; /* Device is allocated */ + const char *device_id; /* Device name */ + dma_device_t device; /* ... to which this channel is attached */ + dma_buf_t *head; /* where to insert buffers */ + dma_buf_t *tail; /* where to remove buffers */ + dma_buf_t *curr; /* buffer currently DMA'ed */ + int stopped; /* 1 if DMA is stalled */ + dma_regs_t *regs; /* points to appropriate DMA registers */ + int irq; /* IRQ used by the channel */ + dma_callback_t callback; /* ... to call when buffers are done */ + + unsigned int queueCnt; + unsigned int usedQueueCnt; + int isSleeping; + int spin_size; /* > 0 when DMA should spin when no more buffer */ + dma_addr_t spin_addr; /* DMA address to spin onto */ + int spin_ref; /* number of spinning references */ + + unsigned char already_init; /* S3C2800 specific */ +} s3c2800_dma_t; + +/* S3C2800 DMA API */ +extern int s3c2800_request_dma( dmach_t channel, const char *device_id, + dma_device_t device ); +extern int s3c2800_dma_set_callback( dmach_t channel, dma_callback_t cb ); +extern int s3c2800_dma_set_spin( dmach_t channel, dma_addr_t addr, int size ); +extern int s3c2800_dma_queue_buffer( dmach_t channel, void *buf_id, + dma_addr_t data, int size ); +extern int s3c2800_dma_get_current( dmach_t channel, void **buf_id, dma_addr_t *addr ); +extern int s3c2800_dma_stop( dmach_t channel ); +extern int s3c2800_dma_resume( dmach_t channel ); +extern int s3c2800_dma_flush_all( dmach_t channel ); +extern void s3c2800_free_dma( dmach_t channel ); +extern int s3c2800_dma_sleep( dmach_t channel ); +extern int s3c2800_dma_wakeup( dmach_t channel ); +extern void s3c2800_dma_done (s3c2800_dma_t *dma); + +#endif /* _ASM_S3C2800_ARCH_DMA_H */ + + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/hardware.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/hardware.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/hardware.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/hardware.h Sat Oct 18 07:02:35 2003 @@ -0,0 +1,28 @@ +/* + * linux/include/asm-arm/arch-s3c2800/hardware.h + * + * Author: + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include + +#ifdef CONFIG_MACH_FUJITSU_CAMELOT + +#define PA_DUAL_PORT_BASE 0x06000000 +#define VA_DUAL_PORT_BASE 0xd1000000 + +#define PA_CAMELOT_BASE 0x04000000 +#define VA_CAMELOT_BASE 0xd2000000 + +#endif + +#endif /* END OF __ASM_ARCH_HARDWARE_H */ + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/io.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/io.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/io.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/io.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,41 @@ +/* + * linux/include/asm-arm/arch-s3c2800/io.h + * + * Author: + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff /* Used in kernel/resource.c */ + +#define PCI_IO_VADDR (0x0) +#define PCI_MEMORY_VADDR (0x0) + +#define __io(a) (PCI_IO_VADDR + (a)) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) (PCI_MEMORY_VADDR + (unsigned long)(a)) + + +/* + * Generic virtual read/write + */ +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) + +/* + * Validate the pci memory address for ioremap. + */ +#define iomem_valid_addr(iomem,size) (1) + + +/* + * Convert PCI memory space to a CPU physical address + */ +#define iomem_to_phys(iomem) (iomem) + +#endif diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/irq.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/irq.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/irq.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/irq.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-s3c2800/irq.h + * + * Author: + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __S3C2800_IRQ_H +#define __S3C2800_IRQ_H + +/* to understand S3C2800 irq, look hard at fixup_irq in irq.c */ +extern unsigned int fixup_irq(int i); + +extern void do_IRQ(int irq, struct pt_regs *regs); + +#endif /* __S3C2800_IRQ_H */ diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/irqs.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/irqs.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/irqs.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/irqs.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,133 @@ +/* + * linux/include/asm-arm/arch-s3c2800/irqs.h + * + * Copyright (C) 2002 SAMSUNG ELECTRONIS + * SW.LEE (hitchcar@sec.samsung.com) + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __S3C2800_IRQS_H +#define __S3C2800_IRQS_H 1 + +/* bits in interrupt register */ +#define BIT_SHIFT_EINT0 (0) +#define BIT_SHIFT_EINT1 (1) +#define BIT_SHIFT_EINT2 (2) +#define BIT_SHIFT_EINT3 (3) +#define BIT_SHIFT_EINT4 (4) +#define BIT_SHIFT_EINT5 (5) +#define BIT_SHIFT_EINT6 (6) +#define BIT_SHIFT_EINT7 (7) +#define BIT_SHIFT_PCI (8) +#define BIT_SHIFT_RESERVED (9) +#define BIT_SHIFT_DMA0 (10) +#define BIT_SHIFT_DMA1 (11) +#define BIT_SHIFT_DMA2 (12) +#define BIT_SHIFT_DMA3 (13) +#define BIT_SHIFT_TIMER0 (14) +#define BIT_SHIFT_TIMER1 (15) +#define BIT_SHIFT_TIMER2 (16) +#define BIT_SHIFT_IIC0 (17) +#define BIT_SHIFT_IIC1 (18) +#define BIT_SHIFT_RXD0 (19) +#define BIT_SHIFT_RXD1 (20) +#define BIT_SHIFT_TXD0 (21) +#define BIT_SHIFT_TXD1 (22) +#define BIT_SHIFT_UERR0 (23) +#define BIT_SHIFT_UERR1 (24) +#define BIT_SHIFT_RMT (25) +#define BIT_SHIFT_FULL (26) +#define BIT_SHIFT_TICK (27) +#define BIT_SHIFT_RTC (28) + +#define IRQ_EINT0 BIT_SHIFT_EINT0 +#define IRQ_EINT1 BIT_SHIFT_EINT1 +#define IRQ_EINT2 BIT_SHIFT_EINT2 +#define IRQ_EINT3 BIT_SHIFT_EINT3 +#define IRQ_EINT4 BIT_SHIFT_EINT4 +#define IRQ_EINT5 BIT_SHIFT_EINT5 +#define IRQ_EINT6 BIT_SHIFT_EINT6 +#define IRQ_EINT7 BIT_SHIFT_EINT7 +#define IRQ_PCI BIT_SHIFT_PCI +#define IRQ_DMA0 BIT_SHIFT_DMA0 +#define IRQ_DMA1 BIT_SHIFT_DMA1 +#define IRQ_DMA2 BIT_SHIFT_DMA2 +#define IRQ_DMA3 BIT_SHIFT_DMA3 +#define IRQ_TIMER0 BIT_SHIFT_TIMER0 +#define IRQ_TIMER1 BIT_SHIFT_TIMER1 +#define IRQ_TIMER2 BIT_SHIFT_TIMER2 +#define IRQ_IIC0 BIT_SHIFT_IIC0 +#define IRQ_IIC1 BIT_SHIFT_IIC1 +#define IRQ_RXD0 BIT_SHIFT_RXD0 +#define IRQ_RXD1 BIT_SHIFT_RXD1 +#define IRQ_TXD0 BIT_SHIFT_TXD0 +#define IRQ_TXD1 BIT_SHIFT_TXD1 +#define IRQ_UERR0 BIT_SHIFT_UERR0 +#define IRQ_UERR1 BIT_SHIFT_UERR1 +#define IRQ_RMT BIT_SHIFT_RMT +#define IRQ_FULL BIT_SHIFT_FULL +#define IRQ_TICK BIT_SHIFT_TICK +#define IRQ_RTC BIT_SHIFT_RTC + +#define NoIntBase 32 /* Normal Interrupt Base */ + +#define IRQ_DUMMY (NoIntBase+1) +#define NR_IRQS (NoIntBase+1) + +//#define OS_TIMER IRQ_TIMER4 /* Used in irq.c */ + +#if 0 +/**************** This External IRQ **********/ +#define IRQ_EINT4 (NoIntBase+0) +#define IRQ_EINT5 (NoIntBase+1) +#define IRQ_EINT6 (NoIntBase+2) +#define IRQ_EINT7 (NoIntBase+3) +#define IRQ_EINT8 (NoIntBase+4) +#define IRQ_EINT9 (NoIntBase+5) +#define IRQ_EINT10 (NoIntBase+6) +#define IRQ_EINT11 (NoIntBase+7) +#define IRQ_EINT12 (NoIntBase+8) +#define IRQ_EINT13 (NoIntBase+9) +#define IRQ_EINT14 (NoIntBase+10) +#define IRQ_EINT15 (NoIntBase+11) +#define IRQ_EINT16 (NoIntBase+12) +#define IRQ_EINT17 (NoIntBase+13) +#define IRQ_EINT18 (NoIntBase+14) +#define IRQ_EINT19 (NoIntBase+15) +#define IRQ_EINT20 (NoIntBase+16) +#define IRQ_EINT21 (NoIntBase+17) +#define IRQ_EINT22 (NoIntBase+18) +#define IRQ_EINT23 (NoIntBase+19) +/*************************************************/ + +#define IRQ_RXD0 (NoIntBase+20) +#define IRQ_TXD0 (NoIntBase+21) +#define IRQ_ERR0 (NoIntBase+22) +#define IRQ_RXD1 (NoIntBase+23) +#define IRQ_TXD1 (NoIntBase+24) +#define IRQ_ERR1 (NoIntBase+25) +#define IRQ_RXD2 (NoIntBase+26) +#define IRQ_TXD2 (NoIntBase+27) +#define IRQ_ERR2 (NoIntBase+28) +#define IRQ_TC (NoIntBase+29) +#define IRQ_ADCDone (NoIntBase+30) /* 62 */ +#define IRQ_DUMMY (NoIntBase+31) +#define NR_IRQS ((NoIntBase+30)+1) +#endif + + +#endif /* __S3C2800_IRQS_H */ diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/memory.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/memory.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/memory.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/memory.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,79 @@ +/* + * linux/include/asm-arm/arch-s3c2800/memory.h + * + * Copyright (C) 2002 SAMSUNG ELECTRONICS + * SW.LEE + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xC0000000UL) + +/* + * Physical SDRAM offset is 0x08000000 on the S3C2800 + */ +#define PHYS_OFFSET (0x08000000UL) + +/* + * We take advantage of the fact that physical and virtual address can be the + * same. The NUMA code is handling the large holes that might exist between + * all memory banks. + */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro + +/* Modified by SW.LEE */ +#define __virt_to_phys(x) ( ((x)- PAGE_OFFSET)+PHYS_OFFSET ) +#define __phys_to_virt(x) ( ((x)- PHYS_OFFSET)+PAGE_OFFSET ) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + * + * + */ +#define __Distance_PA_VA 0x90000000 +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro +#define __virt_to_bus(x) ((x - __Distance_PA_VA)) +#define __bus_to_virt(x) ((x + __Distance_PA_VA)) + + +#define PHYS_TO_NID(addr) (0) /* node 0 */ +#define NR_NODES 1 + /* used in fucntion bootmem_init arch/arm/mm/init.c */ + + + +#endif /* __ASM_ARCH_MEMORY_H */ + + + + + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/param.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/param.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/param.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/param.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,12 @@ +/* + * linux/include/asm-arm/arch-s3c2800/param.h + * + * Author: + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#define HZ 100 diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/s3c2800.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/s3c2800.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/s3c2800.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/s3c2800.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,412 @@ +/* + * linux/include/asm-arm/arch-s3c2800/s3c2800.h + * + * Author: + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __S3C2800_H +#define __S3C2800_H + +/* clock parameters */ +#define FCLK 203000000 +#define HCLK (FCLK/2) +#define PCLK (HCLK/2) + +#if 0 +#define S3C2800_MEM_SIZE (64*1024*1024) +#define MEM_SIZE S3C2800_MEM_SIZE +#define RAMDISK_DN_ADDR 0x08800000 /* used in asm/arch/arch.c */ +#endif + +#define PA_SDRAM_BASE 0x08000000 /* sdram bank 0 */ + + +/* + * S3C2800 internal registers + */ + +/* Be careful !!!! + * PAGE_OFFSET + VMALLOC_END = 0xD0000000 + */ + +#define VA_IO_BASE0 (0xD0000000) +#define VA_IO_BASE1 (0xE0000000) + +#define PA_CKPO_BASE (0x10000000) +#define VA_CKPO_BASE (VA_IO_BASE0+0x00000000) + +#define PA_MEM_CTR_BASE (0x10010000) +#define VA_MEM_CTR_BASE (VA_IO_BASE0+0x00010000) + +#define PA_INT_BASE (0x10020000) +#define VA_INT_BASE (VA_IO_BASE0+0x00020000) + +#define PA_DMA_BASE (0x10030000) +#define VA_DMA_BASE (VA_IO_BASE0+0x00030000) + +#define PA_PCI_BASE (0x10080000) +#define VA_PCI_BASE (VA_IO_BASE0+0x00080000) + +#define PA_IO_PORT_BASE (0x10100000) +#define VA_IO_PORT_BASE (VA_IO_BASE1+0x00100000) + +#define PA_RRCR_BASE (0x10110000) +#define VA_RRCR_BASE (VA_IO_BASE1+0x00110000) + +#define PA_WD_BASE (0x10120000) +#define VA_WD_BASE (VA_IO_BASE1+0x00120000) + +#define PA_TIMER_BASE (0x10130000) +#define VA_TIMER_BASE (VA_IO_BASE1+0x00130000) + +#define PA_RTC_BASE (0x10160000) +#define VA_RTC_BASE (VA_IO_BASE1+0x00160000) + +#define PA_UART_BASE (0x10170000) +#define VA_UART_BASE (VA_IO_BASE1+0x00170000) + +#define PA_IIC_BASE (0x10190000) +#define VA_IIC_BASE (VA_IO_BASE1+0x00190000) + +#define VA_MEM_CTR(offset) (*(volatile unsigned *)(VA_MEM_CTR_BASE+(offset))) + +/* Memory control */ +#define rENDIAN VA_MEM_CTR(0x00) /* endian control */ +#define rSMBCON0 VA_MEM_CTR(0x04) /* bank 0 control */ +#define rSMBCON1 VA_MEM_CTR(0x08) /* bank 1 control */ +#define rSMBCON2 VA_MEM_CTR(0x0c) /* bank 2 control */ +#define rSMBCON3 VA_MEM_CTR(0x10) /* bank 3 control */ +#define rREFRESH VA_MEM_CTR(0x14) /* DRAM/SDRAM refresh control */ +#define rDMTMCON VA_MEM_CTR(0x18) /* dynamic memory timing control */ +#define rMRSR VA_MEM_CTR(0x1c) /* memory mode select */ + + +/* interrupt */ +#define VA_INT(offset) (*(volatile unsigned *)(VA_INT_BASE+(offset))) + +#define rSRCPND VA_INT(0x00) /* Interrupt request status */ +#define rINTMOD VA_INT(0x04) /* Interrupt mode control */ +#define rINTMSK VA_INT(0x08) /* Interrupt mask control */ +#define rIRQPND VA_INT(0x0c) /* IRQ interrupt service pending */ +#define rFIQPND VA_INT(0x10) /* FIQ interrupt service pending */ + + +/* remote control reciever */ +#define VA_RRCR(offset) (*(volatile unsigned *)(VA_RRCR_BASE+(offset))) + +#define rRRCR VA_RRCR(0x00) /* remote control receiver control */ +#define rFIFOD VA_RRCR(0x04) /* fifo data register */ + +/* DMA */ +#define VA_DMA(chan, offset) \ + (*(volatile unsigned *)(VA_DMA_BASE+(0x10000*chan)+(offset))) + +#define VA_DMA_0(offset) VA_DMA(0, offset) +#define VA_DMA_1(offset) VA_DMA(1, offset) +#define VA_DMA_2(offset) VA_DMA(2, offset) +#define VA_DMA_3(offset) VA_DMA(3, offset) + +/* DMA Device Address Reg. channel [0..3] */ +#define DMASp 0x10000 /* DMA control reg. space (bytes) */ +#define ARRAY_DISRC(ch) ((volatile unsigned *)(VA_DMA_BASE+(ch)*DMASp)) + +#define rDISRC0 VA_DMA_0(0x00) /* DMA 0 Initial source */ +#define rDIDST0 VA_DMA_0(0x04) /* DMA 0 Initial Destination */ +#define rDCON0 VA_DMA_0(0x08) /* DMA 0 Control */ +#define rDSTAT0 VA_DMA_0(0x0c) /* DMA 0 Status */ +#define rDCSRC0 VA_DMA_0(0x10) /* DMA 0 Current source */ +#define rDCDST0 VA_DMA_0(0x14) /* DMA 0 Current destination */ +#define rDMASKTRIG0 VA_DMA_0(0x18) /* DMA 0 Mask trigger */ + +#define rDISRC1 VA_DMA_1(0x00) /* DMA 1 Initial source */ +#define rDIDST1 VA_DMA_1(0x04) /* DMA 1 Initial Destination */ +#define rDCON1 VA_DMA_1(0x08) /* DMA 1 Control */ +#define rDSTAT1 VA_DMA_1(0x0c) /* DMA 1 Status */ +#define rDCSRC1 VA_DMA_1(0x10) /* DMA 1 Current source */ +#define rDCDST1 VA_DMA_1(0x14) /* DMA 1 Current destination */ +#define rDMASKTRIG1 VA_DMA_1(0x18) /* DMA 1 Mask trigger */ + +#define rDISRC2 VA_DMA_2(0x00) /* DMA 2 Initial source */ +#define rDIDST2 VA_DMA_2(0x04) /* DMA 2 Initial Destination */ +#define rDCON2 VA_DMA_2(0x08) /* DMA 2 Control */ +#define rDSTAT2 VA_DMA_2(0x0c) /* DMA 2 Status */ +#define rDCSRC2 VA_DMA_2(0x10) /* DMA 2 Current source */ +#define rDCDST2 VA_DMA_2(0x14) /* DMA 2 Current destination */ +#define rDMASKTRIG2 VA_DMA_2(0x18) /* DMA 2 Mask trigger */ + +#define rDISRC3 VA_DMA_3(0x00) /* DMA 3 Initial source */ +#define rDIDST3 VA_DMA_3(0x04) /* DMA 3 Initial Destination */ +#define rDCON3 VA_DMA_3(0x08) /* DMA 3 Control */ +#define rDSTAT3 VA_DMA_3(0x0c) /* DMA 3 Status */ +#define rDCSRC3 VA_DMA_3(0x10) /* DMA 3 Current source */ +#define rDCDST3 VA_DMA_3(0x14) /* DMA 3 Current destination */ +#define rDMASKTRIG3 VA_DMA_3(0x18) /* DMA 2 Mask trigger */ + +/* DMA channel status */ +#define DSTAT_STAT_READY 0x000000 +#define DSTAT_STAT_BUSY 0x100000 + +/* DMA mask trigger register */ +#define DMASKTRIG_STOP 0x4 /* bits 100 */ +#define DMASKTRIG_START 0x0 +#define DMASKTRIG_ON 0x2 /* bits 010 */ +#define DMASKTRIG_OFF 0x0 +#define DMASKTRIG_NO_SW_TRIG 0x0 + +/* DMA control register flag */ +#define DCON_HS_MODE ( 0x1 << 30) +#define DCON_SYNC_AHB ( 0x1 << 29) +#define DCON_INT_ENABLE ( 0x1 << 28) +#define DCON_TSZ_BURST ( 0x1 << 27) +#define DCON_WHSR_MODE ( 0x1 << 26) +#define DCON_HWSRCSEL_I2SDO ( 0x00 << 24) +#define DCON_HW_SEL ( 0x1 << 23) +#define DCON_NO_AUTO_RELOAD ( 0x1 << 22) +#define DCON_DSZ_HWORD ( 0x1 << 20) + + +/* clock & power management */ +#define VA_CKPO(offset) (*(volatile unsigned *)(VA_CKPO_BASE+(offset))) + +#define rPLLCON VA_CKPO(0x00) /* PLL Control */ +#define rCLKCON VA_CKPO(0x04) /* clock generator control */ +#define rCLKSLOW VA_CKPO(0x08) /* slow clock control */ +#define rLOCKTIME VA_CKPO(0x0c) /* PLL lock time counter */ +#define rSWRCON VA_CKPO(0x10) /* software reset control */ +#define rRSTST VA_CKPO(0x14) /* reset status regster */ + +/* clkcon bits */ +#define CLKCON_PCLK (1 << 12) +#define CLKCON_HCLK (1 << 11) +#define CLKCON_PCI (1 << 10) +#define CLKCON_IIC1 (1 << 9) +#define CLKCON_IIC0 (1 << 8) +#define CLKCON_RTC (1 << 7) +#define CLKCON_UART1 (1 << 6) +#define CLKCON_UART0 (1 << 5) +#define CLKCON_DMA23 (1 << 4) +#define CLKCON_DMA01 (1 << 3) +#define CLKCON_TIMER (1 << 2) +#define CLKCON_IDLE_BIT (1 << 1) + +/* UART */ +#define VA_UART(dt, n, offset) \ + (*(volatile dt *)(VA_UART_BASE+(0x10000*t)+(offset))) + +#define VA_UART_0(offset) VA_UART(unsigned, 0, offset) +#define VA_UART_1(offset) VA_UART(unsigned, 1, offset) + +#define VA_UART_0_B(offset) VA_UART(char, 0, offset) +#define VA_UART_1_B(offset) VA_UART(char, 1, offset) + +#define rULCON0 VA_UART_0(0x00) /* UART 0 Line control */ +#define rUCON0 VA_UART_0(0x04) /* UART 0 Control */ +#define rUFCON0 VA_UART_0(0x08) /* UART 0 FIFO control */ +#define rUMCON0 VA_UART_0(0x0c) /* UART 0 Modem control */ +#define rUTRSTAT0 VA_UART_0(0x10) /* UART 0 Tx/Rx status */ +#define rUERSTAT0 VA_UART_0(0x14) /* UART 0 Rx error status */ +#define rUFSTAT0 VA_UART_0(0x18) /* UART 0 FIFO status */ +#define rUMSTAT0 VA_UART_0(0x1c) /* UART 0 Modem status */ +#define rUBRDIV0 VA_UART_0(0x28) /* UART 0 Baud rate divisor */ + +#define rULCON1 VA_UART_1(0x00) /* UART 1 Line control */ +#define rUCON1 VA_UART_1(0x04) /* UART 1 Control */ +#define rUFCON1 VA_UART_1(0x08) /* UART 1 FIFO control */ +#define rUMCON1 VA_UART_1(0x0c) /* UART 1 Modem control */ +#define rUTRSTAT1 VA_UART_1(0x10) /* UART 1 Tx/Rx status */ +#define rUERSTAT1 VA_UART_1(0x14) /* UART 1 Rx error status */ +#define rUFSTAT1 VA_UART_1(0x18) /* UART 1 FIFO status */ +#define rUMSTAT1 VA_UART_1(0x1c) /* UART 1 Modem status */ +#define rUBRDIV1 VA_UART_1(0x28) /* UART 1 Baud rate divisor */ + +#ifdef __BIG_ENDIAN +#define rUTXH0 VA_UART_0_B(0x23) /* UART 0 Transmission Hold */ +#define rURXH0 VA_UART_0_B(0x27) /* UART 0 Receive buffer */ +#else /* Little Endian */ +#define rUTXH0 VA_UART_0_B(0x20) /* UART 0 Transmission Hold */ +#define rURXH0 VA_UART_0_B(0x24) /* UART 0 Receive buffer */ +#endif + +#ifdef __BIG_ENDIAN +#define rUTXH1 VA_UART_1_B(0x23) /* UART 1 Transmission Hold */ +#define rURXH1 VA_UART_1_B(0x27) /* UART 1 Receive buffer */ +#else /* Little Endian */ +#define rUTXH1 VA_UART_1_B(0x20) /* UART 1 Transmission Hold */ +#define rURXH1 VA_UART_1_B(0x24) /* UART 1 Receive buffer */ +#endif + + +/* timer */ +#define VA_TIMER(t, offset) \ + (*(volatile unsigned *)(VA_TIMER_BASE+(0x10000*t)+(offset))) + +#define VA_TIMER_ADDR(t, offset) \ + ((volatile unsigned *)(VA_TIMER_BASE+(0x10000*t)+(offset))) + +#define rTMDMASEL VA_TIMER(0, 0x0c) /* dma or interrupt mode selection */ + +#define VA_TIMER_0(offset) VA_TIMER(0, offset) +#define VA_TIMER_1(offset) VA_TIMER(1, offset) +#define VA_TIMER_2(offset) VA_TIMER(2, offset) + +#define rTMCON0 VA_TIMER_0(0x00) +#define rTMDATA0 VA_TIMER_0(0x04) +#define rTMCNT0 VA_TIMER_0(0x08) + +#define rTMCON1 VA_TIMER_1(0x00) +#define rTMDATA1 VA_TIMER_1(0x04) +#define rTMCNT1 VA_TIMER_1(0x08) + +#define rTMCON2 VA_TIMER_2(0x00) +#define rTMDATA2 VA_TIMER_2(0x04) +#define rTMCNT2 VA_TIMER_2(0x08) + +#define RESCHED_PERIOD 10 /* 10 ms */ + +#define HZ 100 + + +/* watch dog timer */ +#define VA_WD(offset) (*(volatile unsigned *)(VA_WD_BASE+(offset))) + +#define rWTPSCLR VA_WD(0x00) /* Watch-dog timer prescaler value */ +#define rWTCON VA_WD(0x04) /* Watch-dog timer mode */ +#define rWTCNT VA_WD(0x08) /* Eatch-dog timer count */ + + +/* IIC */ +#define VA_IIC(n, offset) \ + (*(volatile unsigned *)(VA_IIC_BASE+(0x10000*n)+(offset))) + +#define VA_IIC_0(offset) VA_IIC(0, offset) +#define VA_IIC_1(offset) VA_IIC(1, offset) + +#define rIICCON0 VA_IIC(0, 0x00) /* IIC control */ +#define rIICSTAT0 VA_IIC(0, 0x04) /* IIC status */ +#define rIICADD0 VA_IIC(0, 0x08) /* IIC address */ +#define rIICDS0 VA_IIC(0, 0x0c) /* IIC data shift */ + +#define rIICCON1 VA_IIC(1, 0x00) /* IIC control */ +#define rIICSTAT1 VA_IIC(1, 0x04) /* IIC status */ +#define rIICADD1 VA_IIC(1, 0x08) /* IIC address */ +#define rIICDS1 VA_IIC(1, 0x0c) /* IIC data shift */ + + +/*-----------------------------------------------------*/ + +/* GPIO ports */ +#define VA_IO_PORT(offset) (*(volatile unsigned *)(VA_IO_PORT_BASE+(offset))) + +#define rPCONA VA_IO_PORT(0x00) /* Port A control */ +#define rPDATA VA_IO_PORT(0x04) /* Port A data */ +#define rPUPA VA_IO_PORT(0x08) /* Pull-up control A */ + +#define rPCONB VA_IO_PORT(0x0c) /* Port B control */ +#define rPDATB VA_IO_PORT(0x10) /* Port B data */ + +#define rPCONC VA_IO_PORT(0x18) /* Port C control */ +#define rPDATC VA_IO_PORT(0x1c) /* Port C data */ +#define rPUPC VA_IO_PORT(0x20) /* Pull-up control C */ + +#define rPCOND VA_IO_PORT(0x24) /* Port D control */ +#define rPDATD VA_IO_PORT(0x28) /* Port D data */ +#define rPUPD VA_IO_PORT(0x2c) /* Pull-up control D */ + +#define rPCONE VA_IO_PORT(0x30) /* Port E control */ +#define rPDATE VA_IO_PORT(0x34) /* Port E data */ +#define rPUPE VA_IO_PORT(0x3c) /* Pull-up control E */ + +#define rPCONF VA_IO_PORT(0x3c) /* Port F control */ +#define rPDATF VA_IO_PORT(0x40) /* Port F data */ +#define rPUPF VA_IO_PORT(0x44) /* Pull-up control F */ + +#define rEXTINTR VA_IO_PORT(0x48) /* External interrupt control register */ +#define rSPUCR VA_IO_PORT(0x4c) /* special pull-up control register */ + +//#define rMISCCR VA_IO_PORT(0x80) //Miscellaneous control +//#define rDCLKCON VA_IO_PORT(0x84) //DCLK0/1 control +//#define rEXTINT1 VA_IO_PORT(0x8c) //External interrupt control register 1 +//#define rEXTINT2 VA_IO_PORT(0x90) //External interrupt control register 2 +//#define rEINTFLT0 VA_IO_PORT(0x94) //Reserved +//#define rEINTFLT1 VA_IO_PORT(0x98) //Reserved +//#define rEINTFLT2 VA_IO_PORT(0x9c) //External interrupt filter control register 2 +//#define rEINTFLT3 VA_IO_PORT(0xa0) //External interrupt filter control register 3 +//#define rEINTMSK VA_IO_PORT(0xa4) //External interrupt mask +//#define rEINTPND VA_IO_PORT(0xa8) //External interrupt pending +//#define rGSTATUS0 VA_IO_PORT(0xac) //External pin status +//#define rGSTATUS1 VA_IO_PORT(0xb0) //Chip ID(0x32800000) +//#define rGSTATUS2 VA_IO_PORT(0xb4) //Reset type +//#define rGSTATUS3 VA_IO_PORT(0xb8) //Saved data0(32-bit) before entering POWER_OFF mode +//#define rGSTATUS4 VA_IO_PORT(0xbc) //Saved data0(32-bit) before entering POWER_OFF mode + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define VA_RTC(offset) (*(volatile char *)(VA_RTC_BASE+(offset)+3)) +#else +#define VA_RTC(offset) (*(volatile char *)(VA_RTC_BASE+(offset))) +#endif + +#define rRTCCON VA_RTC(0x00) /* RTC control */ +#define rRTCALM VA_RTC(0x04) /* RTC alarm control */ +#define rALMSEC VA_RTC(0x08) /* Alarm second */ +#define rALMMIN VA_RTC(0x0c) /* Alarm minute */ +#define rALMHOUR VA_RTC(0x10) /* Alarm Hour */ +#define rALMDAY VA_RTC(0x14) /* Alarm day */ +#define rALMMON VA_RTC(0x18) /* Alarm month */ +#define rALMYEAR VA_RTC(0x1c) /* Alarm year */ +#define rBCDSEC VA_RTC(0x20) /* BCD second */ +#define rBCDMIN VA_RTC(0x24) /* BCD minute */ +#define rBCDHOUR VA_RTC(0x28) /* BCD hour */ +#define rBCDDAY VA_RTC(0x2c) /* BCD day */ +#define rBCDDATE VA_RTC(0x30) /* BCD date */ +#define rBCDMON VA_RTC(0x34) /* BCD month */ +#define rBCDYEAR VA_RTC(0x38) /* BCD year */ +#define rTICNT VA_RTC(0x40) /* Tick time count */ +#define rRTCRST VA_RTC(0x44) /* RTC round reset */ + + +/* PCI */ +#define VA_PCI(offset) (*(volatile unsigned *)(VA_PCI_BASE+(offset))) + +#define rPCIVDIDR VA_PCI(0x00) /* PCI vendor */ +#define rPCISCR VA_PCI(0x04) /* PCI status and command */ +#define rPCICRIDR VA_PCI(0x08) /* PCI class code and revision */ +#define rPCIGCONR VA_PCI(0x0c) /* PCI general control */ +#define rPCIBAR0 VA_PCI(0x10) /* PCI memory bar 0 */ +#define rPCIBAR1 VA_PCI(0x14) /* PCI memory bar 0 */ +#define rPCIBAR2 VA_PCI(0x18) /* PCI memory bar 0 */ +#define rPCISSVIDR VA_PCI(0x2c) /* PCI subsystem */ +#define rPCICPR VA_PCI(0x34) /* PCI subsystem */ +#define rPCIMISCR VA_PCI(0x3c) /* PCI subsystem */ +#define rPCITOR VA_PCI(0x40) /* PCI subsystem */ + +#define rPCICON VA_PCI(0x100) /* PCI control and status */ +#define rPCISET VA_PCI(0x104) /* PCI command */ +#define rPCIINTEN VA_PCI(0x108) +#define rPCIINTST VA_PCI(0x10c) +#define rPCIINTAD VA_PCI(0x110) +#define rPCIATAPM VA_PCI(0x114) +#define rPCIATAPI VA_PCI(0x118) +#define rPCIBELAP VA_PCI(0x128) +#define rPCIATPA0 VA_PCI(0x140) +#define rPCIBAM0 VA_PCI(0x144) +#define rPCIATAPA1 VA_PCI(0x148) +#define rPCIBAM1 VA_PCI(0x14c) +#define rPCIATAPA2 VA_PCI(0x150) +#define rPCIBAM2 VA_PCI(0x154) + +/* Used in serial_s3c2800.c ,uncompress.h */ +#define SER_BAUD_9600 9600 +#define SER_BAUD_19200 19200 +#define SER_BAUD_38400 38400 +#define SER_BAUD_57600 57600 +#define SER_BAUD_115200 115200 +#define CURRENT_BAUD_RATE SER_BAUD_115200 + +#endif /* __S3C2800_H */ diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/system.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/system.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/system.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/system.h Sat Oct 18 07:05:59 2003 @@ -0,0 +1,77 @@ +/* + * linux/include/asm-arm/arch-s3c2800/system.h + * + * Copyright (C) 2002 SAMSUNG ELECTRONICS + * SW.LEE + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +/* + * This functions used in arm/kernel/process.c + */ + +#ifdef CONFIG_LEDS +extern void set_led_state(int); +#endif + +static void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt ticks + */ +#ifndef CONFIG_LEDS + cpu_do_idle(0); +#else + int i; + rCLKCON |= CLKCON_IDLE_BIT; /* enter idle mode for a moment */ + for (i = 0; i < 100; i++); + rCLKCON &= ~CLKCON_IDLE_BIT; +#endif + +} + +static inline void arch_reset(char mode) +{ + /* use the watchdog timer reset to reset the processor */ + + /* (at this point, MMU is shut down, so we use physical addrs) */ + volatile unsigned long *prWTCON = (unsigned long*) (PA_WD_BASE + 0x00); + volatile unsigned long *prWTDAT = (unsigned long*) (PA_WD_BASE + 0x04); + volatile unsigned long *prWTCNT = (unsigned long*) (PA_WD_BASE + 0x08); + + /* set the countdown timer to a small value before enableing WDT */ + *prWTDAT = 0x00000100; + *prWTCNT = 0x00000100; + + /* enable the watchdog timer */ + *prWTCON = 0x00008021; + + /* machine should reboot..... */ + + mdelay(5000); + panic("Watchdog timer reset failed!\n"); + printk(" Jump to address 0 \n"); + cpu_reset(0); +} + +#endif diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/time.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/time.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/time.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/time.h Sat Oct 18 07:06:02 2003 @@ -0,0 +1,125 @@ +/* + * linux/include/asm-arm/arch-s3c2800/time.h + * + * Copyright (C) SAMSUNG ELECTRONICS + * SW.LEE + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +extern unsigned long (*gettimeoffset)(void); + +static unsigned long last_TMCNT2; + +/* + * Returns microsecond since last clock interrupt. + * Note that interrupts will have been disabled by do_gettimeoffset() + * IRQs are disabled before entering here from do_gettimeofday() + */ +static unsigned long s3c2800_gettimeoffset(void) +{ + unsigned long elapsed,usec; + + /* + * tick is microsecond unit + * long tick = (1000000 + HZ/2) / HZ; timer interrupt period + * kernel/timer.c + */ + + elapsed = last_TMCNT2 - rTMCNT2; + + /* + * A SIMPLE RATIO + * (elapsed / rTMCNT2) = ( usec / tick ) + */ + + /* + * IF YOU WANT TO USE LATCH + * SEE arch-s3c2800/timex.h + * it gave me troubles + */ + + usec = (elapsed * tick) / last_TMCNT2; + + return usec; +} + + +/* + * IRQ handler for the timer + */ +static void s3c2800_timer_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + long flags; + + if (0) printk("s3c2800_timer_interrupt()\n"); + do_leds(); + save_flags_cli( flags ); + do_timer(regs); + restore_flags( flags ); + do_set_rtc(); + do_profile(regs); +} + +/* + * Set up timer interrupt, and return the current time in seconds. + */ + +static inline void setup_timer(void) +{ + gettimeoffset = s3c2800_gettimeoffset; + + if (0) printk("setup_timer()\n"); + + timer_irq.handler = s3c2800_timer_interrupt; + + rTMDMASEL = 0; + +#define SYS_TIMER2_PRESCALER 125 +#define SYS_TIMER2_COUNT 1015 + +#define SYS_TIMER2_MUX_1_4 0x0 /* 1/4 */ +#define SYS_TIMER2_INT_DMA_ENA 0x2 +#define SYS_TIMER2_COUNT_ENA 0x1 + + /* pclk 50750000 / (125 * 4 * 1015) = 100 = 10ms */ + + rTMCON2 = SYS_TIMER2_MUX_1_4 | SYS_TIMER2_INT_DMA_ENA; + rTMDATA2 = SYS_TIMER2_COUNT | (SYS_TIMER2_PRESCALER << 16); + + /* be cautious, TMCNT2 be below 2^16=65535 [15:0] */ +// last_TMCNT2 = (RESCHED_PERIOD * PCLK) / +// ((SYS_TIMER2_PRESCALER+1) * 4 * SYS_TIMER2_COUNT * 1000); + + last_TMCNT2 = SYS_TIMER2_COUNT; + + printk("setup_timer: PCLK %x (%d), last_TMCNT2 0x%x\n", + PCLK, PCLK, last_TMCNT2); + + /* rTMCNTB2 = X second * (frequency/second) */ +// rTMCNT2 = last_TMCNT2; + + /* setup up irq function */ + setup_arm_irq(IRQ_TIMER2, &timer_irq); + + /* start timer 2 */ + rTMCON2 |= SYS_TIMER2_COUNT_ENA; + + if (0) printk("setup_timer() done\n"); +} diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/timex.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/timex.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/timex.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/timex.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,31 @@ +/* + * linux/include/asm-arm/arch-s3c2800/timex.h + * + * Copyright (C) 2002 SAMSUNG ELECTRONICS + * SW.LEE + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (PCLK/((SYS_TIMER234_PRESCALER +1)*(SYS_TIMER4_DIVIDER))) + +/* TIP by SW.LEE + * + * LATCH == rTCNTB4 = (RESCHED_PERIOD/1000)* + * (PCLK/((SYS_TIMER234_PRESCALER +1)*(SYS_TIMER4_DIVIDER))) + * LATCH == ((CLOCK_TICK_RATE + HZ/2) / HZ) + * + */ diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/uncompress.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/uncompress.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/uncompress.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/uncompress.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,148 @@ +/* + * linux/include/asm-arm/arch-s3c2800/uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* physical addresses */ +#define PA_GPIO_BASE 0x10100000 +#define PA_UART_BASE 0x10170000 + +/* gpio ports */ +#define rPCONA (*(volatile unsigned *)(PA_GPIO_BASE+0x00)) //Port A control +#define rPDATA (*(volatile unsigned *)(PA_GPIO_BASE+0x04)) //Port A data +#define rPUPA (*(volatile unsigned *)(PA_GPIO_BASE+0x04)) //Port A data + +#define rPCONB (*(volatile unsigned *)(PA_GPIO_BASE+0x0c)) //Port B control +#define rPDATB (*(volatile unsigned *)(PA_GPIO_BASE+0x10)) //Port B data + +#define rPCONC (*(volatile unsigned *)(PA_GPIO_BASE+0x18)) //Port C control +#define rPDATC (*(volatile unsigned *)(PA_GPIO_BASE+0x1c)) //Port C data +#define rPUPC (*(volatile unsigned *)(PA_GPIO_BASE+0x20)) //Pull-up control C + +#define rPCOND (*(volatile unsigned *)(PA_GPIO_BASE+0x24)) //Port D control +#define rPDATD (*(volatile unsigned *)(PA_GPIO_BASE+0x28)) //Port D data +#define rPUPD (*(volatile unsigned *)(PA_GPIO_BASE+0x2c)) //Pull-up control D + +#define rPCONE (*(volatile unsigned *)(PA_GPIO_BASE+0x30)) //Port E control +#define rPDATE (*(volatile unsigned *)(PA_GPIO_BASE+0x34)) //Port E data +#define rPUPE (*(volatile unsigned *)(PA_GPIO_BASE+0x38)) //Pull-up control E + +#define rPCONF (*(volatile unsigned *)(PA_GPIO_BASE+0x3c)) //Port F control +#define rPDATF (*(volatile unsigned *)(PA_GPIO_BASE+0x40)) //Port F data +#define rPUPFF (*(volatile unsigned *)(PA_GPIO_BASE+0x44)) //Pull-up control F + +#define rSPUCR (*(volatile unsigned *)(PA_GPIO_BASE+0x4c)) //Special pull-up control + +/* level trigger and edge trigger */ +#define rEXTINTR (*(volatile unsigned *)(PA_GPIO_BASE+0x48)) //External interrupt control register + +/* UART */ +#define rULCON0 (*(volatile unsigned *)(PA_UART_BASE+0x00)) //UART 0 Line control +#define rUCON0 (*(volatile unsigned *)(PA_UART_BASE+0x04)) //UART 0 Control +#define rUFCON0 (*(volatile unsigned *)(PA_UART_BASE+0x08)) //UART 0 FIFO control +#define rUMCON0 (*(volatile unsigned *)(PA_UART_BASE+0x0c)) //UART 0 Modem control +#define rUTRSTAT0 (*(volatile unsigned *)(PA_UART_BASE+0x10)) //UART 0 Tx/Rx status +#define rUTXH0 (*(volatile unsigned char *)(PA_UART_BASE+0x20)) + +#define rUBRDIV0 (*(volatile unsigned *)(PA_UART_BASE+0x28)) //UART 0 Baud rate divisor + +#define SER_BAUD_9600 9600 +#define SER_BAUD_14400 11400 +#define SER_BAUD_19200 19200 +#define SER_BAUD_38400 38400 +#define SER_BAUD_57600 57600 +#define SER_BAUD_115200 115200 +#define CURRENT_BAUD_RATE SER_BAUD_115200 + +/* clock parameters */ +#define FCLK 202800000 +#define HCLK (FCLK/2) +#define PCLK (HCLK/2) + +/********************************************/ + + +/* led on chamelot board */ +static void led_display(int data) +{ + rPDATF = (data & 0xf) << 4; +} + +static void uart_putc(int data) +{ + if (data == '\n') + uart_putc('\r'); + + /* wait until THR is empty */ + while (!(rUTRSTAT0 & 0x2)) + ; +{ volatile long l; for (l = 0; l < 5000; l++); } + + rUTXH0 = data; +} + +static void putc(const char c) +{ + uart_putc(c); +} + +static void puts(const char *s) +{ + while (*s) + uart_putc(*s++); +} + + +static void uart_init(int pclk, int baud) +{ + rUFCON0 = 0x0; /* UART 0 FIFO control register, FIFO disable */ + rUMCON0 = 0x0; /* UART 0 MODEM control register, AFC disable */ + rULCON0 = 0x3; + rUCON0 = 0x245; /* control register */ + rUBRDIV0 = ((int)(pclk/16/baud) - 1); /* baud rate div register 0 */ + + { + volatile int i; + for (i = 0; i < 100; i++) ; + } +} + +#define arch_decomp_wdog() + +static void port_init(void) +{ + /* setup gpio's */ + rPCONA = 0x0000003f; + rPCONB = 0x0000f0ff; + rPCONC = 0x00000000; + rPCOND = 0x00000f0f; + rPCONE = 0x00000000; + rPUPE = 0x000000ff; + rPCONF = 0x0000550f; + +#if 0 + /* external interrupt will be falling edge triggered. */ + rEXTINTR = 0x00000000; +#endif +} + +static void arch_decomp_setup() +{ + port_init(); + led_display(6); + uart_init(PCLK, CURRENT_BAUD_RATE); +} + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/vmalloc.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/vmalloc.h --- linux-2.4.21-rmk1/include/asm-arm/arch-s3c2800/vmalloc.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/arch-s3c2800/vmalloc.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-s3c2800/vmalloc.h + * + * Copyright (C) 2000 SAMSUNG ELECTRONICS + * SW.LEE + * 2003 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define MAX_S3C2800_SDRAM_SIZE (0x10000000) + +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + MAX_S3C2800_SDRAM_SIZE) diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/asm-arm/hardware/serial_s3c2800.h linux-2.4.21-rmk1-s3c2800/include/asm-arm/hardware/serial_s3c2800.h --- linux-2.4.21-rmk1/include/asm-arm/hardware/serial_s3c2800.h Wed Dec 31 19:00:00 1969 +++ linux-2.4.21-rmk1-s3c2800/include/asm-arm/hardware/serial_s3c2800.h Thu Oct 16 10:33:11 2003 @@ -0,0 +1,85 @@ +/* + * linux/include/asm-arm/hardware/serial_s3c2800.h + * + * Internal header file for Samsung S3C2800 serial ports (UART0 & UART1) + * + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * + * Adapted from: + * + * Internal header file for S3C2410 serial ports (UART1 & 2) + * Internal header file for MX1ADS serial ports (UART1 & 2) + * + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef ASM_ARM_HARDWARE_SERIAL_S3C2800_H +#define ASM_ARM_HARDWARE_SERIAL_S3C2800_H + +#define S3C2800_UARTRXH0_OFF (0x24) +#define S3C2800_UARTTXH0_OFF (0x20) +#define S3C2800_UARTLCON_OFF (0x00) +#define S3C2800_UARTCON_OFF (0x04) +#define S3C2800_UARTFCON_OFF (0x08) +#define S3C2800_UARTMCON_OFF (0x0C) +#define S3C2800_UARTBRDIV_OFF (0x28) +#define S3C2800_UARTTRSTAT_OFF (0x10) +#define S3C2800_UARTERSTAT_OFF (0x14) +#define S3C2800_UARTFSTAT_OFF (0x18) +#define S3C2800_UARTMSTAT_OFF (0x1C) + + +#define S3C2800_UART1_OFF (0x10000) + +#define S3C2800_LCON_CFGMASK ((0xF<<3)|(0x3)) + +#define S3C2800_LCON_CS5 (0x0) +#define S3C2800_LCON_CS6 (0x1) +#define S3C2800_LCON_CS7 (0x2) +#define S3C2800_LCON_CS8 (0x3) + +#define S3C2800_LCON_PNONE (0x0) +#define S3C2800_LCON_PEVEN ((0x5)<<3) +#define S3C2800_LCON_PODD ((0x4)<<3) + +#define S3C2800_UCON_SBREAK (1<<4) + +#define S3C2800_UCON_TXILEVEL (1<<9) +#define S3C2800_UCON_RXILEVEL (1<<8) +#define S3C2800_UCON_TXIRQMODE (1<<2) +#define S3C2800_UCON_RXIRQMODE (1<<0) +#define S3C2800_UCON_RXFIFO_TOI (1<<7) + +#define S3C2800_UCON_DEFAULT (S3C2800_UCON_TXILEVEL \ + | S3C2800_UCON_RXILEVEL \ + | S3C2800_UCON_TXIRQMODE \ + | S3C2800_UCON_RXIRQMODE \ + | S3C2800_UCON_RXFIFO_TOI) + +#define S3C2800_UFCON_FIFOMODE (1<<0) +#define S3C2800_UFCON_TXTRIG0 (0<<6) +#define S3C2800_UFCON_RXTRIG8 (1<<4) +#define S3C2800_UFCON_RXTRIG12 (2<<4) + +#define S3C2800_UFCON_DEFAULT (S3C2800_UFCON_FIFOMODE | \ + S3C2800_UFCON_TXTRIG0 | \ + S3C2800_UFCON_RXTRIG12 ) + +#define S3C2800_UTRSTAT_TXFE (1<<1) +#define S3C2800_UTRSTAT_RXDR (1<<0) + +#endif /* ASM_ARM_HARDWARE_SERIAL_S3C2800_H */ + diff -urN --exclude=CVS --exclude='.*' linux-2.4.21-rmk1/include/linux/serial_core.h linux-2.4.21-rmk1-s3c2800/include/linux/serial_core.h --- linux-2.4.21-rmk1/include/linux/serial_core.h Thu Oct 16 10:10:12 2003 +++ linux-2.4.21-rmk1-s3c2800/include/linux/serial_core.h Sat Oct 18 07:03:17 2003 @@ -72,6 +72,7 @@ #define PORT_OMAHA 48 #define PORT_AT91RM9200 49 +#define PORT_S3C2800 50 #ifdef __KERNEL__