Notes by Colin Cross, colincross at bigfoot.com
4/19/02

Main Board Jumper Connectors
----------------------------

    10 9 8 7 6
    -----------
    |* * * * *|       
J5  |         |
    |* * * * *|
    -----------
     1 2 3 4 5

1:  DCD (37)
2:  TX1 (32)
3:  Gnd
4:  PD6 (54)
5:  PA4 (26)
6:  +5V
7:  CTS (35)
8:  DSR (38)
9:  PD7 (53)
10: RX1 (36)

               
              J8
       1 1 1 1
    14 3 2 1 0 9 8
    ---------------
    |* * * * * * *|       
    |             |
    |* * * * * * *|
    ---------------
     1 2 3 4 5 6 7

1:  VCC??
2:  nTRST (pin 125, pulled up 1K)
3:  TDI (pin 11, pulled up 1K)
4:  TMS (pin 58, pulled up 1K)
5:  TCLK (pin 90, pulled up 1K)
6:  PA3 (pin 27, pulled up 1K)
7:  VCC??
8:  Gnd
9:  nPOR (pin 154, connected to pin 9 of U17)
10: Gnd
11: Gnd
12: Gnd
13: Gnd
14: Gnd

    ----
   1|* |
J10 |  |
    | *|2
    ----
1: nMEDCHG/nBOR pin 155, pulled up through R119 (10K)
2: Gnd
Short these two pins to go to Boot ROM mode! Yay!


LCD Controller
--------------
in ISA mode (MD1, MD3 pulled high externally by R78 and R79, MD2 pulled low internally)
I think # and N___ mean inverted

MD on rising edge of RESET:
10000010 11011010

AB[20:0] on LCD controller connected to A[20:0] on ARM
DB[20:0] on LCD controller connected to D[20:0] on ARM
RD# connected to NMOE
WE0# connected to NMWE
WE1# connected to VCC
RD/WR# connected to VCC
RESET# connected to PD1
WAIT# connected to EXPRDY
CS# connected to NCS2
M/R# connected to A21
BS# connected to VCC
BUSCLK: R31 pulldown (0.5K), connected through R6 (47ohm) to output of inv. 
	in U13, input of inverter connected to EXPCLK through R60 (22ohm)

WE1 is the SHBE# signal: when asserted, it signals that the upper half of the data bus, D[15:8], will be used to transfer a byte between the microprocessor and an odd address. 

CLKI from EXPCLK on ARM inverted through U13

Memory Chip Selects
-------------------
0: Flash memory (1MB)
1: Flash memory (1MB)
2: LCD Controller

Power Up Sequence
-----------------

     ---------------------------
     |           U13           |
     |   R65     |\     R67    |   U20
     |--/\/\/\---| >o--/\/\/\------,--,    R71
     |           |/    47 ohm       )  )o-/\/\/\--- WAKEUP
    ---C59                PD0 -----'--'
    ---102nF
     |
    ---                            
     -
nURESET connected to VCC with R14
nPOR connects to pin 1 of U2 (labeled 815B), pin 2 GND, pin 3 VCC
S1 (not soldered on) pulls nPOR low

Backlight Control
-----------------
PD5 high=backlight on

PD5 connects to R114

Q8 NPN, top pin gate connected to PD5

PWM outputs on CPU (DRIVE0 and DRIVE1) control brightness
DRIVE0 controls backlight brightness level
       inverted and smoothed to produce control input to backlight inverter
       15/16 darkest
       0/16 brightest
DRIVE1 should be at 50% (LCD contrast??)
For a good start, set PMPCON to 0x800 (50% contrast, full brightness)

----
PD2 goes to pin 8 of U21 (part of the soft modem)