Description of mpc860hdlc Linux network device driver.

HDLC encapsulation on TDM timeslots using MPC860T Linux-running hardware.

Functional Description.

This low-level driver can be used by a generic HDLC driver (hdlc.c ) to run various point-to-point protocols over TDM link. The driver is designed for the proprietary DGT-LAB Cross-Connect WAN blade. This blade is based on Motorola MPC 860T Communication Processor. There is no framer/ line adapter on this board, but other components of the Cross-Connect system are responsible for generating clock/frame sync signals and interfacing internal TDM signals to the outside word. Therefore if you want to use the driver on a different hardware containing MPC860, you must write your own framer / physical interface control. On the WAN blade, MPC860T's Time Slot Assigner is connected to 2 TDM 2Mbit buses. Currently, only the bus connected to B part of TSA can be used (this makes dynamic timeslots assignment impossible). 2048 kHz external clock and 8 kHz frame synchronization signals are supplied to the blade. The MPC860T's Communication Processor ports are connected almost directly to Cross-Connect's TDM switch. Dedicated timeslots of TDM or V.35 physical interface can be used to connect WAN blade to the other side of the link (e.g. to Cisco 2600 router, which has been used for evaluation). Currently driver supports 2 point-to-point interfaces but it is possible to create 4 such interfaces (using all 4 SCCs of MPC860T).

Detailed hardware specification.

MPC860T port (pin) assignment is presented here. If you want to use the driver with hardware with different port assigmnent, you should modify code.

Connected to 2048kHz clock:

L1RCLKA-PA7

L1TCLKA-PA5

L1RCLKB-PA2

L1TCLKB-PA0

Connected to 8kHz frame sync pulses:

L1RSYNCA-PC4

L1TSYNCA-PC5

L1RSYNCB-PC6

L1TSYNCB-PC7

Connected to tristate input of TDM bus transmitter (strobe)

L1ST1-PB19 (channel A)

L1ST2-PB18 (channel B)

Connected to TDM bus A

L1RXDA-PA8

L1TXDA-PA9

Connected to TDM bus B

L1RXDB-PA10

L1TXDB-PA11

Driver configuration and usage.

The driver supports run-time loading.

When driver is dynamically loaded, it supports debug mode (printing debug messages). To enable this feature, use insmod mpc860hdlc debug=1. The second debug mode ( debug=2) allows printing physical hdlc frames sent and received by the driver. Note however that kernel printk mechanism can only be used for debugging purpose. Turning on debug mode impairs driver's performance. Printk buffers may be overrun if this function is abused.

Driver configuration is performed after loading by sethdlc utility. Communication between sethdlc utility and mpc860hdlc + generic hdlc drivers is achieved via ioctls, defined in <linux/hdlc.h>. Some commands are used internally by higher-level hdlc driver. It is not possible to open hdlc0 or hdlc1 interface without setting protocol on the interface (hdlc, cisco, ppp etc.) and assigning timeslots. The ioctl commands for timeslots assignment (command: slotmap <map>) is HDLCSSLOTMAP and is consumed by mpc860hdlc driver. After performing driver configuration, interface can be activated / deactivated using ifconfig (driver's methods open and close). Setting line (commands: v35[-lb] | rs232[-lb] | x21[-lb] | t1[-lb] | e1[-lb] | lb | default) and clock (command: clock (<rate> | int | ext | txint | txfromrx ) makes no sense for mpc860hdlc driver. HDLCRUN (run) command is also undefined since there is no code to download on firmware. The driver supports standard mechanism for traffic and error counting (counters are defined in struct net_device_stats in <linux/netdevice.h> ).

Notes about driver's internal design.

Currently the driver uses double-buffer copying mechanism. Received data is copied to internal receive buffer by SCC, using DMA. sk_buf allocation and data copying is performed by receiver interrupt - when transfer is finished. Transmitted data is copied to internal transmit buffer and sk_buf is immediately released. If all transmit buffers are full, transmitter buffer queuing is stopped. sk_buff copying is resumed when internal transmit buffer is freed by transmitter interrupt. Transmit and receive buffers are organized in circular queues. Each buffer has is own, statically assigned, buffer descriptor in Communication Processor dynamic memory. This design is very simple, but not very effcient. If there is any problem with performance, the driver will be redesigned to avoid double copying.