StrongARM sdram & rom setup
MDCNFG 0x7254 7255
7
twr21 0
twr20 1
tdl21 1
tdl20 1
2
trp23 0
trp22 0
trp21 1
trp20 0
5
cdb22 0
drac22 1 14, bank 2 & 3
drac21 0
drac20 1
4
dwid2 0
dtim2 1
de3 0 disabled, bank 3
de2 0 disabled, bank 2
7
twr01 0 01, write recovery
twr00 1
tdl01 1 11, cas latency 3 clocks
tdl00 1
2
trp03 0 2
trp02 0
trp01 1
trp00 0
5
cdb20 0 0, sdram
drac02 1 101, 14 row address bits
drac01 0
drac00 1
5
dwid0 0 32 bit
dtim0 1 sdram
de1 0 bank 1 disabled
de0 1 bank 0 enabled
--------
MDREFR = 0x4dbc0327
4
slfrsh 0
x 1
kapd 0
eapd 0 auto power down enable
d
x 1
k2db2 1
k2run 0
x 1
b
x 1
k1db2 0
k1run 1
e1pin 1 sdclk enable
c
x 1
k0db2 1 sdclk0 runs at half speed
k0run 0
e0pin 0
0
dri11 0 0x032; # of clock cycles/32 between
dri10 0 cas before ras refresh cycles
dri9 0
dri8 0
3
dri7 0
dri6 0
dri5 1
dri4 1
2
dri3 0
dri2 0
dri1 1
dri0 0
7
trasr3 0 7; why so high? should be 1 for sdram?
trasr2 1
trasr1 1
trasr0 1
-----------
MDCAS00
MDCAS20 = 0xAAAAAA7F
MDCAS01
MDCAS21 = 0xAAAAAAAA
MDCAS02
MDCAS22 = 0xAAAAAAAA
-----------
/* Static memory chip selects on Assabet: */
MCS0 = 0x00004b90 /* MCS0 */
0
rrr1_2
rrr1_1
rrr1_0
rdn1_4
0
rdn1_3
rdn1_2
rdn1_1
rdn1_0
0
rdf1_4
rdf1_3
rdf1_2
rdf1_1
0
rdf1_0 0
rbw1 0
rt1_1 0 type = 0
rt1_0 0
4
rrr0_2 0 recovery time
rrr0_1 1 010 = 2
rrr0_0 0
rdn0_4 0 rom delay next access
b
rdn0_3 1
rdn0_2 0 01011 = 11 cycles
rdn0_1 1
rdn0_0 1
9
rdf0_4 1 rom delay first access
rdf0_3 0 10010 = 18 cycles
rdf0_2 0
rdf0_1 1
4
rdf0_0 0
rbw0 1 rom bus wid; 0=32 bit, 1=16
rt0_1 0 rom type; flash
rt0_0 0
------------------
MCS1 = 0x22212419 /* MCS1 */
2
rrr3_2 0 recovery time
rrr3_1 0 001 = 1
rrr3_0 1
rdn3_4 0 rdn = 00010
2
rdn3_3 0
rdn3_2 0
rdn3_1 1
rdn3_0 0
2
rdf3_4 0 rdf = 00100
rdf3_3 0
rdf3_2 1
rdf3_1 0
1
rdf3_0 0
rbw3 0
rt3_1 0 type = 01
rt3_0 1
2
rrr2_2 0 recovery time
rrr2_1 0 001 = 1
rrr2_0 1
rdn2_4 0 rom delay next access
4
rdn2_3 0
rdn2_2 1 00100 = 4 cycles
rdn2_1 0
rdn2_0 0
1
rdf2_4 0 rom delay first access
rdf2_3 0 00011 = 3 cycles
rdf2_2 0
rdf2_1 1
9
rdf2_0 1
rbw2 0 rom bus wid; 0=32 bit, 1=16
rt2_1 0 rom type = 01
rt2_0 1
--------------
MCS2 = 0x42196669 /* MCS2 */
4
rrr5_2 0 recovery time
rrr5_1 1 010 = 2
rrr5_0 0
rdn5_4 0 rom delay next access
2
rdn5_3 0 00010 = 2
rdn5_2 0
rdn5_1 1
rdn5_0 0
1
rdf5_4 0 rom delay first access
rdf5_3 0 00011 = 3
rdf5_2 0
rdf5_1 1
9
rdf5_0 1
rbw5 0 rom bus wid; 0=32 bit, 1=16
rt5_1 0 type = 01
rt5_0 1
6
rrr4_2 0 recovery time
rrr4_1 1 011 = 3
rrr4_0 1
rdn4_4 0 rom delay next access
6
rdn4_3 0
rdn4_2 1 00110 = 6 cycles
rdn4_1 1
rdn4_0 0
6
rdf4_4 0 rom delay first access
rdf4_3 1 01101 = 13 cycles
rdf4_2 1
rdf4_1 0
9
rdf4_0 1
rbw4 0 rom bus wid; 0=32 bit, 1=16
rt4_1 0 rom type = 01
rt4_0 1
----------------
SMCNFG = 0xafccafcc /* SMCNFG */
/* Set up PCMCIA space */
MECR = 0x994a994a