Before you can start using a new WearARM board, software must be programmed into the flash memory. This is done via the JTAG port. A device (the JTAG buffer board) is connected between the JTAG port of the WearARM and a PC's parallel port. A linux application is run on the PC which drives the parallel port pins to accesses the StrongARM's JTAG port.
The JTAG port allows access to the processor bus in a very low level manner. The jtag program (the linux application) basically clocks the state of all the pins into the processor in a serial manner. Because it can control all of the processor pins, it can program the flash chips in the same way software running on the processor would (but much more slowly).
A cable needs to be constructed to connect the 8 pin ribbon connector on the "core" cpu card to the 8 pin ribbon connector on the buffer board. It can't be a "straight through" cable, however, as the signals don't quite line up.
Power is applied to J4, +3.3v & +5v
I left J3 unconnected.
The PC parallel port is connected to J2 as below:
J2 signal pc parllel port pin 1 tck 2 data[0] 2 tdo 11 busy 3 tms 4 data[2] 4 tdi 3 data[1] 5 trst 5 data[3] 6 gnd 20,21,24,25 ground
Note that the buffer board I got was not "plated through", so that via's needed to be plugged with a wire and soldered on both sides of the board. Basically, you need to trace each and every signal and make sure you believe it matches the schematic.
J1 8 pin header -> to core module, the "red connector" 1 tclk 2 udc- 3 tdo 4 udc+ 5 tms 6 gnd 7 tdi 8 trst_n J2 6 pin -> to PC parallel port 1 tck 2 tdo 3 tms 4 tdi 5 trst 6 gnd J3 4 pin -> function usb port 1 5v 2 D+ 3 D- 4 GND J4 3 pin -> power; +3.3, +5, gnd 1 +5v 2 +3v 3 gnd From the top of the buffer board: +-------------------------------+ | 1 2 3 4 | | J3 6 | | 1 2 5 | | 3 4 J1 J2 4 | | 5 6 3 | | 7 8 2 | | J4 1 | | 3 2 1 | +-------------------------------+