Blog Archive: March 2024
Domain crossing techniques to avoid metastability in an FPGA
On March 30th, 2016 In Hardware
I recently did some work on a working FPGA design. It suffered from some classic clock domain crossing issue, but despite that it "worked". But when stressed slightly it stopped working.
I first wrote a classic verilog testbench. I'll talk about those in an another post. When I fixed the clock domain crossings the